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Placing different voltage regions together

Posted: 28 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:multiple voltages? IC design? verification? SPICE? simulations?

Using multiple voltages on a single die has been a reality for quite a long time.

Whether you need to mix high-voltage analogue with low-voltage memory, or mix multiple VDDs on the same digital chip, you have to deal with the impact of multiple voltages on the integrity of your layout and your circuit. Also, whether you are concerned more about signal integrity or long-term reliability, the fundamental question becomes C how close can I put these different voltage regions before there are problems?

In the past, the simplest way to deal with the problem of multiple voltages on the same die was to put a marker layer on top of the layout for each region so that everyone knew "this area is using Voltage X," and "this area is using Voltage Y." The design and verification tools then use the marker layer in their operations, and everything works just fine (figure 1).

Figure 1: Using marker layers to identify regions using different voltage potentials.

This approach worked very well for designs that have only a few different voltages, and the layout for the different voltage regions could be neatly contained within well-defined blocks. Also, this method depends on the designer knowing what is in each region and putting the appropriate marker layer on it...and also assumes that they have time to do so and don't forget.

Of course, life in the IC design world isn't quite so simple any longer. There are more voltages, and many, many more power domains. Also, to save space on your die, you may need to route high-voltage lines through areas that are predominantly low-voltage. These factors demand finer granularity and control, which calls for a polygon-level voltage-dependent DRC checking methodology. The idea is quite simple C instead of putting a marker layer over an area, simply put voltage information on the polygons so that the verification tools can calculate the most appropriate spacing rule based on the actual min/max voltage range that a pair of neighbouring polygons will experience. See figure 2 for a simple depiction.

Figure 2: Polygon-level voltage information for voltage-dependent DRC.

When using such a methodology, the DRC tool can use the actual min/max voltage information to decide which minimum spacing rule to apply. For instance, if the maximum possible voltage difference between two adjacent lines is 1.5V, then apply spacing X rule. If the maximum voltage difference is 2.1V, then apply spacing Y rule. With this type of polygon-level checking, it is possible to minimise the required area for a circuit, and ensure that the manufacturing limits are obeyed.

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