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Envisioning better protocol debug

Posted: 29 May 2015 ?? ?Print Version ?Bookmark and Share

Keywords:debug? verification? IP? embedded software? SoC?

The many wheels of technology, as much as we'd like them to, do not move ahead in lockstep fashion. Sometimes the demands of one technology outrun the benefits of an enabling technology.

Take debug: It's a time sink. It consumes half the overall verification effort. On average, it takes engineers three to five cycles through the debug loop to isolate and fix a single bug. A big reason for the increase in debug time seen during the past decade is that designs have gotten significantly more complex, involving sophisticated object-oriented programming-based test benches, third-party IP, and embedded software running on many cores.

You'd think that as design complexity has increased that debug, as a supporting technology, would have advanced in parallel to meet the evolving challenges. But this isn't the case. In fact many engineers are today using the same traditional debug process that's been in place for 20 years: code, simulate, analyse some waveforms, debug. Repeat. Repeat. Repeat however many times it takes.

Now let's layer on another challenge facing today's SoC designers: Interface standards. PCI Express, USB, Ethernet, ARM's Advanced Microcontroller Bus Architecture (AMBA), and the Double Date Rate (DDR) memory interface have become universally deployed standards in recent years. As they have, the conformity of design imposed by these standards drove a huge end-product economy of scale, resulting in a vast array of interoperable hardware and software components. That's the good news.

The bad news is that designing with these interface standards was once a relatively simple step in the design process that's now grown into a multi-headed beast not easily leashed. Why? Because these few standards have sprouted many variations.

Take, for example, DDR memory: A single specification in the year 2000, it today boasts 15 different variations. ARM's AMBA now has eight variations. And the list goes on.

Verifying these standard interfaces has to be done, and that process has grown like kudzu into one of the most resource-intensive tasks for verification engineers. And that's a problem because verification engineers seldom have more than a couple weeks to ramp up on a new protocol before they have to start verifying designs incorporating it.

"The diversification of standard interfaces is a legitimate trend, something that people have to deal with," said Moshik Rubin, product marketing director from Cadence. "And it makes the debugging process that much more difficult for verification engineers."

Verification IP (VIP) takes much of the strain out of this, but it's not enough amid this interface explosion.

Let's examine what this looks like in practice: Let's say you're designing a new controller chip that's going into an external disc drive and it needs a USB interface on it. You start to simulate that, and your verification IP flags an error: The chip issued a command and the host on the computer (played, in this case, by the VIP) issued another command. It says "hey your chip responded with wrong response."

The verification engineer, dealing with SystemVerilog code for his test bench, looks at the long string of packets received by VIP to try to determine the problem. At this point, the pressure's on him to translate the design behaviour and protocol specification requirements to figure out the root cause.

With the release of the new Indago Protocol Debug App on the Indago Debug Platform, engineers now have a way of understanding their design behaviour in the context of the protocol specifications to help understood the root cause of the problem.

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