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Designing phase adjustable PA for 5G front-ends

Posted: 10 Aug 2015 ?? ?Print Version ?Bookmark and Share

Keywords:5G? transmitter? power amplifier? phase shifter? Simulations?

The PA output (to the right of the layout image) comprises 4 power combined transistors, driven from a pair of power-combined transistors of the same size. The 4bit phase shifter is positioned before this with an input stage of amplification that is a modified version of the 2 transistor driver stage. Vd1, Vd2 and Vd3 are the drain supplies for the power amplifier and they are nominally set to +6V. Vg1 sets the quiescent bias current in the first stage and Vg23 in the second and third stages.

The phase state of each bit of the integrated phase shifter is controlled by a single-ended TTL compatible control line. All of the control logic required to shift the levels to those needed for the phase shifter bits is included on-chip.

Single channel performance
The performance plots presented below are at room temperature, nominal bias across the frequency range 26 C 30GHz.

The 4bit phase shifter is based on a switched high-pass/low-pass filter topology [3]; it allows the insertion phase of each channel to be independently set with 22.5 resolution. The most significant bit of the phase shifter (180) uses two Single Pole Double Throw (SPDT) switches to route the RF signal through either a high pass or a low pass filter. The phase through the high pass filter is advanced compared to the low pass filter with the phase difference being relatively constant over a reasonable bandwidth. Optimisation of the component values is required to obtain the desired phase difference with an acceptable amplitude difference. The lower order bits make use of re-configurable phase shifter bits, in which individual filter components are selectively bypassed with switching elements rather than switching between two different filter networks. This configuration offers the benefit of lower insertion loss.

A plot of the simulated phase shift versus frequency for each of the 16 states of a single channel, including the PA, is shown in figure 3; the desired flat phase shift versus frequency response is clearly evident.

Figure 3: Phase shift versus frequency for a single channel.

With all digitally controlled phase shifters there is always a (hopefully) small phase difference between the phase shift produced by a certain phase setting and the ideal phase shift that would be produced if each bit were perfect. The RMS phase error is a statistical measure of this deviation, used to quantify the accuracy of the phase setting, and is plotted against frequency in figure 4 showing a worst case of 2.38occurring at around 27.5GHz.

Figure 4: RMS phase shift error versus frequency for a single channel.

The gain of each channel of the transmitter IC is just over 20 dB (excluding the splitting losses of the 4-way in-phase splitter). Gain variation across all 16 phase states is less than 0.6 dB at 28GHz. The total gain variation with both frequency (over 26 to 30GHz) and all phase states is 1.5 dB.

An ideal phase shifter would have an amplitude response that did not change with phase state. In reality there will always be some change in amplitude associated with a change in phase state. At 28GHz the RMS amplitude error of each channel of this IC is just 0.2 dB.

As the phase state of a multi-bit, digitally controlled phase shifter changes the reflected waves from each bit experience different phase shifts as they travel back towards the input. Sometimes the reflected waves add constructively at the input, so degrading return loss, sometimes they add destructively, so improving return loss. All multi-bit phase shifters exhibit significant variation in return loss with phase state [3]; the input and output return losses versus frequency for a single channel of this design are plotted in figure 5 for all phase states. Although significant variation in return loss with phase state is evident, the worst case return loss is still good. The worst case return loss across the 26 to 30GHz range occurs at 26GHz for both input and output. At the input the worst case return loss is 13.4 dB and at the output it is slightly higher at 14.9 dB.

Figure 5: Input and output match versus frequency for a single channel, all phase states.

The quiescent bias current of the complete 3-stage PA is 626mA from +6V. Each PA can provide an RF output power at 1 dB gain compression (P-1dB) of 30 dBm at 28GHz. Across the 26 to 30GHz band the P-1dB is nominally +29.5 dBm with a variation of

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