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Agile techniques for hardware design (Part 1)

Posted: 24 Aug 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Software? Waterfall development model? hardware? FPGA? Agile?

Software used to be developed as a sequence of distinct phases, each of which can take six or more months:

1. Requirements analysis and specification
2. Architectural design
3. Implementation and integration
4. Verification and test
5. Operation and maintenance

This process is the called the Waterfall development model, since it flows from the top down to completion. Waterfall relies on extensive documentation, planning, and using PERT and Gantt charts to try to make the schedule match the budget.

So many software projects were late, over budget, or abandoned that it led to a revolution in software development, demarcated by the Agile Manifesto in 2001. Agile development embraces change as a fact of life; small teams continuously refine a working but incomplete prototype until the customer is happy with the result. What to do in the next iteration depends on the evaluation of the current one, as opposed to some master plan established at the beginning of the project. Thus, the elaborate planning and documentation of the Waterfall process is moot.

While highly controversial when it was announced, today most software projects use Agile, and these projects are indeed much more likely to be completed on time and on budget. One survey found that percentage of software projects that were on-time and on-budget, late or over budget, or cancelled went from 10% / 52% / 38% for Waterfall to 76% / 20% / 4% for Agile.

It would seem that frequent prototypes are incompatible with hardware development. Just the mask costs for a chip design today are on the order of multiples of millions of dollars, and a widely used estimate for the development of a system-on-a-chip is $30 to $100 million. This argument is made by the many whose hardware designs rely on standard parts, such as FPGAs.

The good news is that organisations like MOSIS still offer multi-project wafers where many independent projects are put on the same reticle to help amortise mask costs. The large chips are then diced into many small ones for the different projects. A typical use today is to make test chips for the analogue portions of a big chip before taping it out.

While the four-month latency for fabrication and evaluation of such a shuttle run may seem lethargic to software engineers, it still allows three to ten times more iterations than the one- to three-year latency of Waterfall. Moreover, we supplement our prototype tape-outs with what we call "tapeins," where we do all the checks to get the design ready for tape-out, but instead just go on to the next iteration. Thus, between real tape-outs and tapeins, iterations can be a month long or less.

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