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DSP-enhanced MCUs, SoCs target wireless designs

Posted: 07 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Microchip? DSP? MCU? SoC? wireless?

Chip vendors with innovative DSP-enhanced MCU and SoC designs are aiming at the next generation of wireless, wearable IoTs and various video and audio related consumer designs. In fact, there is a predicable rhythm to MCU and processor-based SoC product introductions in those segments of the electronics market focused on consumer wireless, video, and mobile PC/laptop designs.

It starts in early fall shortly after original equipment manufacturers have rolled out their designs for the Christmas market, all based on technologies demonstrated by IC makers at the previous January Consumer Electronics Show (CES). This is followed by chip vendors who are already rolling out new components and designs they want to show off at the next CES, where they hope to get enough attention from OEMs to end up in products for the following year's next Christmas market.

It's now fall, and based on what chip vendors are talking to me about, my guess is that next year's big consumer designs will centre around applications requiring more powerful digital signal processing capabilities. The first to roll out such ICs and processors include companies such as Ensilica, Flex Logix, Microchip and Synopsys.

Synopsys makes a DSP bid with ARC EM9D/11D

The most recent and most impressive rollout so far out is the Synopsys DesignWare ARC EM9D and EM11D processor cores. They have a DSP enhanced version of the ARCv2DSP instruction set architecture (ISA) and have added an X-Y memory system to boost digital signal processing performance while minimising power consumption.

"We've designed our new cores for a range of IoT applications in the consumer wireless and wearable IoT space, where we expect vendors will be need a lot of DSP capabilities but within very constrained power budgets," said Angela Raucher, product line manager, ARC EM Processors.

To accomplish that, all of the EM DSP cores incorporate a three- rather than -five-stage pipeline to achieve lower power consumption. But to make up for possible loss of performance, the architecture makes use of separate X and Y memory blocks. This allows a system to more closely track and more efficiently process regular data access patterns common in signal processing code. "This architecture is most useful for DSP applications needing fast memory accesses while performing repeated mathematical operations on arrays of numbers," said Raucher.

DSP-enhanced MCUs, SoCs

Target of chip vendors with DSP add-ons to their MCUs and SoC is the next generation of wireless wearable IoTs and a range of video and audio related consumer designs.

Raucher explained that on-chip address generation units provide additional addressing modes that make complex address calculations independently, removing a significant overhead from the CPU and ensuring efficient memory access without cycle penalties. When used in combination with enhanced direct memory access to more efficiently move data in and out of the block memory, the EM9D/EM11D is able to achieve a sustained throughput of one 32x32 MAC operation or two 16x16 MAC operations per clock cycle with minimal energy and area overhead.

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