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ATPG sol'n from Synopsys expedites test pattern generation

Posted: 08 Oct 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? test pattern generation? ATPG? debug?

Synopsys Inc. has unleashed what it describes as a breakthrough automatic test pattern generation (ATPG) and diagnostics technology that delivers 10X faster run time and 25 per cent fewer test patterns to reduce schedules, speed up silicon debug, and minimise test time and cost. Combined with Synopsys' DFTMAX compression, this test technology will enable design teams to meet their test quality, time and cost goals with exceptional speed, boasted the company.

According to Synopsys, the test generation, fault simulation and diagnosis engines are fast, exceedingly memory efficient and highly optimised for generating patterns and executing fine-grained multithreading of the ATPG and diagnosis processes. These innovations lead to fewer test patterns and 10X faster runtime, enable utilisation of all server cores regardless of design size and surpass previous technologies that are limited by high memory usage. Moreover, tight links with Synopsys' Galaxy Design Platform tools, such as Design Compiler RTL Synthesis, PrimeTime timing signoff and StarRC parasitic extraction, along with other Synopsys tools, including Yield Explorer yield analysis and Verdi automated debug system, deliver remarkable quality test while decreasing turnaround time, added the company.

The Synopsys synthesis-based test solution is comprised of SpyGlass DFT ADV testability analysis, DFTMAX, DFTMAX Ultra and TetraMAX power-aware logic test and silicon diagnostics offerings; the DesignWare STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System solution for embedded test, repair and diagnostics; the Yield Explorer tool for design-centric yield analysis; and the Camelot software system for CAD navigation.

The Synopsys test solution delivers tight integration across the Synopsys Galaxy Design Platform, including Design Compiler, IC Compiler II place and route system, and PrimeTime, to enable faster turnaround time meeting both design and test goals, higher defect coverage and faster yield ramp.





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