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ISSCC to see advancements in vision processors, 3D chips

Posted: 17 Nov 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Samsung? Intel? vision processors? 3D chip? SRAM?

A description of the talk admits "there are growing concerns and doubts over the vitality of Moore's Law going forward, given the scaling challenges we face." Besides describing Intel's current 14nm process, the "talk will also discuss some leading technology options on the horizon beyond CMOS and their potential design benefits in advancing Moore's Law well into the future. Novel 3D heterogeneous integration schemes and new memory technologies will be discussed for their potential in optimising the memory hierarchy and addressing bandwidth challenges in processor performance and power," according to the ISSCC materials.

3D stacks rise above Moore's Law challenges

The increasing cost and complexity of making chips is driving companies to explore 3D stacks as an alternative way to gain performance or lower power.

Samsung will describe a stack of up to eight DRAM chips that delivers bandwidth of 307Gb/s, more than double a 128Gb/s stack described at ISSCC 2014. Samsung put a phase-lock loop on the 20nm chip to ease testing of the device. To lower heat, it uses "an adaptive refresh scheme considering the [chip's] temperature distribution," the paper description said.

Rival SK Hynix will show a DRAM stack delivering 256Gb/s. The chip handles "command decoding and bias generation for the memory core...[at the] logic base-layer of the stack" instead of at the memory layer as in previous designs. In addition, it uses "small swing signaling on the heavily loaded [3D interconnect] to reduce power for driving the interconnects."

Such dense memory chips will "enable high performance computing, accelerators and small form factor graphics cards" said ISSCC organisers.

A separate Samsung paper will describe a 256Gb flash chip storing three bits per cell and using an on-die stack of 48 cell layers. Samsung has been pioneering such monolithic stacks in flash design, showing a route to denser chips without needing more aggressive process technologies.

Rival Micron aims to leapfrog Samsung's work, describing a 768Gb flash chip with a 64KB page buffer in 179.2mm2 die area. It "achieves the highest density NAND flash memory by placing the peripheral circuits under the array."

Such dense chips will help drive the market for solid-state disks that is expected to be worth more than $20 billion in 2016, said ISSCC organisers.

The CEA-LETI research institute in France also will shine a light on chip stacking technology with a paper describing a novel 4x4x2 asynchronous network-on-chip for a 3D circuit built in a 65nm process. The chip is aimed at advanced cellular network gear and "achieves the lowest energy consumption on 3D I/O power supply at 0.32pJ/b, and the highest data rate at 326Mb/s," researchers said.

Better fingerprint recognition, machine vision

ISSCC also will describe advances in several application areas from fingerprint recognition to machine vision and DNA sequencing.

A team from Invensense and the University of California will describe an ultrasonic fingerprint sensor using "a 110x56 PMUT array bonded to a CMOS chip that delivers a 431x582dpi image in 2.64ms while consuming just 280?J."

"Its unique ability to image both the surface epidermis and sub-surface dermis fingerprint make it insensitive to perspiration and resistant to spoofing, enabling highly robust, low-cost personal ID sensing" in mobile devices, ISSCC organisers said.

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