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Place and route sol'n passes Samsung's 10nm qualification

Posted: 27 Nov 2015 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? place and route solution? Samsung? 10nm? FinFET?

Synopsys Inc. has revealed that its IC Compiler II place and route solution has been qualified for Samsung Foundry's latest 10nm process. A successor to the IC Compiler launched last year, IC Compiler II claims to be the industry's leading place-and-route solution for advanced design.

IC Compiler II was designed and built from the ground up to deliver game-changing improvements in throughput and designer productivity, stated the company. IC Compiler II is in broad use on Samsung Foundry's 14nm production FinFET process by a number of mutual customers resulting in numerous completed tape-outs at this node. Driven by this success at 14nm and increasing customer demand, Samsung Foundry accelerated enablement of IC Compiler II for their latest 10nm process and expedited its qualification.

Based on this rigorous qualification programme, Samsung and mutual customers can now realise the many transformational benefits of IC Compiler II on the 10nm FinFET process. IC Validator's run set availability for this 10nm node enables the In-Design flow with IC Compiler II, which shortens time-to-tapeout and significantly reduces the timing impact of metal fill, added the company.

The foundation of the IC Compiler II includes data-model, library and infrastructure advances that maximise multi-core and multi-machine scalability. Through patented advanced-abstraction and compact data-encapsulation, this scalability delivers the capacity for beyond five hundred-million placeable instance design planning tasks while concurrently delivering more than 5X physical implementation throughput. With quality of results (QoR) a key focus for IC Compiler II, variation-tolerant clock-building techniques and the industry's first analytical-physical-synthesis engine deliver proven timing, area and power QoR benefits. Key for 10nm designs, support for lithography-aware placement constraints, fully colour-aware routing as well as timing and extraction modeling are natively captured throughout the infrastructure, enabling all critical IC Compiler II implementation engines to deliver a highly convergent physical-design solution.





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