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Minimising risk through hardware emulation

Posted: 30 Dec 2015 ?? ?Print Version ?Bookmark and Share

Keywords:hardware emulation? risk? RTL? debugging? processor?

Risk aversion, which comes from the uncertainty associated with committing a design to silicon, is the name of the game. Software developers, hardware designers and verification engineers have arrived at this conclusion and rely on hardware emulation to debug an SoC design's hardware and software. It can be used for all types of hardware designs (with the exception of anything analogue) ranging in size from one-million to more than one-billion ASIC equivalent gates.

The "Big Three" EDA vendors offer hardware emulators in their product portfolios, each with a distinct architecture to give development teams more options. One vendor chose to employ a processor-based architecture; the second, a custom emulator-on-chip architecture; while the third employs a commercial FPGA-based architecture. All three have gained market acceptance.

These vendors recognise the effectiveness of these powerful machines, and have added new features and improved capabilities in 2015. Dynamic power consumption provides one example. As another, emulation has become a data centre resource through a transaction-based emulation mode or acceleration mode, a capability that's met the approval of many development teams.

Long gone are the spaghetti wires running from the emulator box, a risk themselves for lowering the reliability of the system. These days, a hardware emulator is a stylish, sleek box with fewer cables to manage.

I have no doubt that hardware emulation is the way to avoid risk for SoC design debugging. In 2016, you can expect more updates from me from the hardware emulation world, including new capabilities, applications and even a few case studies. Meanwhile, Happy Holidays!

- Lauro Rizzatti
??EE Times


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