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How to prevent latchup in CMOS chips

Posted: 15 Feb 2016 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? power supply? analogue-to-digital converter? ADC? Latchup?

Having voltage on the inputs with power off will cause latchup in a more indirect way. No current can flow in the glass gate insulation. What happens is that the current flows in the internal ESD diodes that are needed to protect the input pin (figure 6). Here the device is operating as a simple two-transistor buffer. Figure 6 builds off the simplicity of figure 4, since the IC designer's tricks are not pertinent to this analysis. The lower ESD protects the part against negative voltage pulses on the input. If you imagine the input pad being drawn negative, you can see current will flow from the P+ pad connected to ground to the N+ pad that has a negative voltage. The current flows directly in the substrate, so the substrate is full of carriers. Once again, if you apply power to the part, those free carriers will seek ground and Vcc through the emitters of the parasitic transistors. With enough free carriers, enough beta, and enough shunt resistance, the part will latch.

Figure 6: The ESD diodes used to protect the pins on a CMOS chip will also cause latchup problems. If you drag the input pin above power or below ground it will inject free carriers into the substrate of the ESD diode structures. When those carriers seek Vcc and ground via the emitters of the parasitic NPN and PNP transistors they can cause the part to enter latchup.

For the case where you drag the input pad to a voltage above Vcc, you are forward biasing that top ESD diode structure. It sits in an N-well and the IC designer will make sure that N-well is separate from the one he used for the P-channel transistor. Nevertheless, there is yet another parasitic vertical PNP formed by the ESD diode structure. So once again, the substrate gets an injection of free carriers. Sure, the ESD diode powers the part as it pulls up the Vcc node, and maybe your power system has low impedance when it is off, so that Vcc node lags a bit, but once you apply real power to the Vcc line, those free carriers in the substrate seek power and ground, and that causes the part to latch.

You can see why latchup is the bane of CMOS IC designers. I once saw a brilliant IC designer struggle for months to keep his op amp design from latching up. He never did solve it. I asked why he was having such problems; after all, the power group had used this exact process for a successful part. He pointed out that a switching regulator was a bandgap reference, a comparator, and an output driver. An op amp has a lot more circuitry and a lot of different structures and transistors and devices in the die. The op amp group had other engineers look at the problem, but ultimately they realised they just could not use that process for amplifiers.

You need to understand the mechanisms and problems of latchup since it is your responsibility to make your designs work. There is nothing the IC designer can do if you abuse his part. It is the IC designer's job to know the input and output structures, and all the really complicated stuff in between. But as a system person, you have to at least understand the input and output structures since that is what your discrete components and cables are connected to. Your complexity resides in the interactions between all the input and output structures in your design.

I once got a call from a famous test equipment company. Their German subsidiary was selling a factory sensor that they would power up, take a measurement, and then power down. The problem was, the op amp in the design would not work for seconds, and then would finally settle down and start working. But the company wanted to take readings in a few milliseconds so they could shut the device down and save power.

I hooked a very fast oscilloscope (made by the company in question) to the circuit. I used JFET probes since they do not load the circuit with as much stray capacitance as a regular probe. It was then apparent that there was an input to the op amp that went to a volt before the op amp Vcc line started to rise. The company had put a very large tantalum capacitor on the power line. I went to that self-same IC designer that had struggled with latchup on his design. He pointed out that the part was well-designed and recovered gracefully from the latchup, but the fact that the ESD diode was forward biased for a few nanoseconds still would put a multitude of free carriers into the substrate. I noted the part did not hard latch, but was just not a functional op amp for a few seconds. He pointed out that modern semiconductor processes are really pure, so that it takes a lot of time for the holes and electrons in the substrate to recombine, and that might well be on the order of a second or two. In the meantime, those free carriers were screwing up the operation of every transistor in the amplifier, so it was no surprise it did not work for a few seconds.

To fix the problem I removed the tantalum decoupling capacitor from the design. Now the op amp Vcc line came up faster than the input to the operational amplifier. There was still a ceramic capacitor to provide decoupling and keep the part out of oscillation. You can imagine the delight of the test equipment company when I told them they could fix the problem by taking out the tantalum capacitors and reducing the cost of their product.

You too can be a hero and miracle-working troubleshooter if you understand just a little of what goes on inside a modern CMOS integrated circuit.

About the author
Paul Rako is with Atmel Corp.


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