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Xilinx sol'n eases logic cell system interconnect bottlenecks

Posted: 21 Apr 2016 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? logic cell? ADAS? 5G? software defined network?

Xilinx Inc. has unveiled the 2016.1 release of the Vivado Design Suite HLx editions with extensions to the SmartConnect technology. According to the company, the solution provides exceptional levels of performance for the UltraScale and UltraScale+ devices.

In the latest release, Vivado Design Suite includes extensions to the SmartConnect technology, solving the system interconnect bottlenecks on high density, multi-million system logic cell designs. As a result, both UltraScale and UltraScale+ device line-ups deliver an additional 20-30 per cent performance at high utilisation.

The Xilinx UltraScale+ portfolio is the only FinFET based programmable technology available in the industry. It includes Zynq, Kintex and Virtex UltraScale+ devices, and delivers 2-5X performance/watt improvement over 28nm offerings, enabling market-leading applications such as 5G wireless, software defined networks and next-generation advanced driver-assistance systems (ADAS).

The Xilinx SmartConnect technology includes a system interconnect IP, as well as optimisations enabled by the UltraScale+ silicon innovations.

Xilinx rolled out its latest system connectivity generator, integrating peripherals to the user design. The AXI SmartConnect IP creates a custom interconnect that best matches the user's system performance requirements, thereby achieving higher system throughput at a lower area and power footprint. The AXI SmartConnect IP is available in Early Access via Vivado IP Integrator in the 2016.1 release of the Vivado Design Suite.

Time borrowing and useful skew optimisations are enabled by the UltraScale+ fine-grain clock delay insertion capability. These fully automated features mitigate large wire delays and deliver designs running at higher clock frequencies, by shifting available timing slack from the fastest paths to the critical paths of the design.

In addition, pipeline analysis and retiming techniques allow designers to further increase performance, by adding extra pipeline stages in the design and applying automatic register retiming optimisation.

The Vivado Design Suite HLx editions and embedded software development tools 2016.1 release are available for download.





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