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Memory/Storage??

Data inspection techniques for massive memory designs

Posted: 02 May 2016 ?? ?Print Version ?Bookmark and Share

Keywords:data storage? DDR? Hybrid Memory Cube? High Bandwidth Memory? Memory Controller?

The Port Scoreboard will compare Read against Write from eight MC Ports & DDR Scoreboard will do the same from two Memory interfaces. As per scenario B, there may not be any Read Transactions since there is a probability of defect in design due to address issued from MC Port getting changed by the time it reaches DDR Memory. If there is no Read transaction, then the Port or DDR Scoreboard will not compare data. If the address is changed when it reaches DDR memory, it will still compare Read data against Write correctly on both Port & DDR Scoreboard independently but with different addresses. So there is a need for second level of address & data checking where Port & DDR Transactions are checked against each other in Port -DDR Compare Scoreboard. In scenario C, uninitialized Read is accessed so default values should be initialized across all locations so that accessed default data will be Read again with warning. The next few sections describe how UVM methodology features & System Verilog constructs have helped build an efficient Verification Environment. The reader can get more details on System Verilog from Reference [1] and on UVM from Reference [2] & [3].

Virtual sequencer & analysis port in UVM
Virtual Sequencer: As shown in figure 2, a UVM-based Verification component is attached to MC Port interface which will generate bursts of Write & Read Transactions. It has a Sequencer which issues transactions to the Driver which will drive a Design Port interface. As each Port interface is independent of the other, the Virtual Sequencer is used to coordinate timing and data between multiple ports. As shown in Figure 2 & the following code, all ports sequencer are controlled from virtual sequencers alone. Port 1 & 2 is initiating Write & Read Transaction on the same address on lower DDR while Port 7 & 8 on upper DDR with more delay on Read Transaction, will ensure it reaches after Write as per Port priority in arbitration logic.

env.virtual_sequencer.port_1_sqr=port_1.sequencer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
env.virtual_sequencer.port_8_sqr=port_8.sequencer
fork
#10 `uvm_do_on_with(port_1_seq, port_1_sqr, {port_1_seq.addr == 34'h0_0000_0100; port_1_seq.typ ==WR})
#100 `uvm_do_on_with(port_2_seq, port_2_sqr, {port_2_seq.addr == 34'h0_0000_0100; port_2_seq.typ ==RD})
#20 `uvm_do_on_with(port_7_seq, port_7_sqr, {port_7_seq.addr == 34'h2_0000_0100; port_7_seq.typ ==WR})
#200 `uvm_do_on_with(port_8_seq, port_8_sqr, {port_8_seq.addr == 34'h2_0000_0100; port_8_seq.typ ==RD})
join

Analysis Port: MC Port Verification components Monitor will capture Transaction on Port interface while DDR Transaction Capture component will capture the same information in DDR Memory interface as shown in Figure 2. UVM Analysis Port is used to send Transactions from all eight Ports interfaces to Port Scoreboard & from two Memory interfaces to DDR Scoreboard. Analysis Port can broadcast to multiple connectors hence same Transactions are also send to Coverage Group.

port_1.monitor.port_ip_analysis_port connect(port_scoreboard.item_collected_export_port_1);
port_1.monitor.port_ip_analysis_port.connect (coverage_collector. cov_collect_port_1);
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
port_8.monitor.port_ip_analysis_port.connect(port_scoreboard.item_collected_export_port_8);
port_8.monitor.port_ip_analysis_port.connect (coverage_collector.cov_collect_port_8);
ddr_1.monitor.mon_analysis_port.connect(ddr_scoreboard. item_collected_export _ddr_1); ddr_2.monitor.mon_analysis_port.connect(ddr_scoreboard. . item_collected_export _ddr_2);
ddr_1.monitor.mon_analysis_port.connect(coverage_collector .cov_collect_ddr_1); ddr_2.monitor.mon_analysis_port.connect(coverage_collector .cov_collect_ddr_2);

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