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Designing POL regulator input filter

Posted: 19 May 2016 ?? ?Print Version ?Bookmark and Share

Keywords:POL regulators? power switch? capacitor? switching regulator? intermediate bus converter?

Phase spreading
When multiple POL regulators share a common DC input supply, it is desirable to adjust the clock phase offset of each device such that not all devices have coincident rising edges. In order to enable phase spreading, all converters must be synchronised to the same switching clock.

In the phase spreading supply, the parallel regulators are switched at specific phase angles. The angles are evenly distributed so that a maximum ripple current cancellation can be achieved. A general equation for the input capacitor RMS current, ICi,RMS, can be approximated as:

Equation 8

where: m=floor(N*D). The floor function returns the greatest integer less than or equal to the input value, N*D, and N is the number of active phases.

Figure 8: Normalized RMS input ripple current versus duty cycle.

Figure 8 shows the normalized input ripple current RMS value over the load current versus duty cycle with different number of active phases.

As can be seen from Equation 7 and figure 8, the input ripple current cancellation is related to the number of phases and duty cycle. Greater ripple reduction is generally achieved with additional phases. Large ripple current will cause very high power dissipation in the input capacitors due to the capacitor ESR. The capacitor lifetime also will be reduced. In addition to the reduction of the input RMS current, the peak-to-peak current is also reduced due to interleaving.

The switching current in the input capacitor is typically a large source of high frequency noise. With the reduced switching current amplitude, the current slew rate is reduced while providing the AC current to the high-side MOSFET. Hence, the noise is reduced. The input ripple frequency will also be higher than that of single-phase operation. The higher frequency makes the input filter smaller and less costly.

The required input capacitance to reduce the ripple voltage amplitude to an acceptable level with phase spreading is defined in Equation 8.

Equation 9

The Vi,pp is the acceptable input voltage ripple contributed by the amount of input capacitance, of which is the input capacitors that filter most of pulsating currents.

The input voltage ripple induced by the ESR of the input capacitor, ESRi, can be estimated with Equation 10.

Equation 10

As it can be seen from Equation 9, phase spreading can dramatically reduce input capacitance requirements.

About the author
Bob Cantrell is Senior Application Engineer at Ericsson Power Modules.


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