Global Sources
EE Times AsiaWebsite
Stay in touch with EE Times Asia
eeBlogs-Article content Home?/?eeBlog?/?eeBlogs
Nickname:?Clive Maxfield???? Articles(444)???? Visits(533461)???? Comments(79)???? Votes(236)???? RSS
There is so much amazingly cool "stuff" to see and do that I'm amazed I find the time to get any real work done. In my blog I will waffle on about the books I'm reading, the projects I'm building, and the weird and wonderful websites I blunder across. Please Email Me if you see anything you think will "tickle my fancy."
Blog Archive
2016?-? Apr.,?? Mar.,?? Feb.,?? Jan.??
2015?-? Dec.,?? Nov.,?? Oct.,?? Sep.,?? Aug.,?? Jul.,?? Jun.,?? May.,?? Apr.,?? Mar.,?? Feb.,?? Jan.??
2014?-? Dec.,?? Nov.,?? Oct.,?? Sep.,?? Aug.,?? Jul.,?? Jun.,?? May.,?? Apr.,?? Mar.,?? Feb.,?? Jan.??
View All
Comment?|?Add to Favorites

Posted: 07:52:10 PM, 30/12/2012

Learn about System Hyper Pipelining

? ?

A few days ago, I heard from my friend Tobias Strauch, the founder of EDAptix in Munich Germany. Well, I'm still trying to wrap my brain around this one...

It seems that for the past few years Tobias has been working on a rather cool technology called System Hyper Pipelining in which he uses registers to multiply the functionality of IP cores.

In his own words, the example Tobias gives is as follows: "You can usually get only one ARM-compatible core (e.g. Amber from OpenCores) on a Spartan-6 LX9 FPGA running at 60MHz. With System Hyper Pipelining I can multiply this functionality and run 16 cores with an equivalent system performance of 250MHz!"

If you are interested in learning more about this technology, Tobias invites you to bounce over to and take a look around. In particular, he says you should check out the technology video.

Tobias also has a demo that runs on his low-cost FPGA Arduino board, an image of which I just snagged from the left-hand side of his projects page at


As part of a spirited email conversation, Tobias added the following:

Maybe I should clarify the 250MHz a little bit. The following rules exist in the demo:

1. You have to run 5 ARMs.
2. Each processor runs at a maximum speed of 50MHz (*5 = 250MHz),
3. You can distribute the 250MHz among up to 16 ARMs
4. Any intermediate scenario is possible (3 @ 50MHz + 5 @ 20MHz = 250MHz).

Tobias is really excited about this C he feels that this System Hyper Pipelining technology is revolutionary, especially when you compare it with the fact that a single ARM only runs at 60MHz.

The problem, he says, is that this technology is so cool that it is very hard to explain and/or sell to people, which is why (a) he created his demo and (b) he asked me to spread the word (grin).

Please do bounce over to and take a look around, and then comment below to tell us what you think.


Label: arm fpga mcu
Views(740) Comments(0)
Total [0] users voted ????
[Last update: 07:54:31 PM, 30/12/2012]
Have Your Say!

Bloggers Say

Got something to say? Why not share it with other engineers?

Just introduce yourself to us, we'll contact you and set you up. Yes, it's that simple!

See what engineers like you are posting on our pages.

Interviews & Viewpoints


Learn how senior executives are seeing the industry from interviews and contributed opinions.

Back to Top