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Posted: 11:21:03 PM, 13/07/2011

The real score on the Intel-TSMC 3-D 'race'

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What's not to love about an account that plays off semiconductor process technology leaders Intel Corp. and Taiwan Semiconductor Manufacturing Co. (TSMC) against one another in a race to achieve some high-level technical goal?

Last week, a report by the Taiwan External Trade Development Council (TAITRA), a nonprofit organization promoting trade with Taiwanese firms, did just that, issuing a report that tantalizingly suggested that TSMC might beat Intel to the punch in bringing "three-dimensional chips" to market. EE Times and other news organizations quickly seized on the report and published stories based on it.

The problem, as many EE Times readers promptly pointed out, is that the report was deeply flawed and based upon a false equivalency. While Intel is preparing to later this year bring to market chips with 3-D transistors (known as tri-gate transistors by Intel), TSMC and others have been working to develop 3-D technology based on through-silicon vias (TSVs), vertical connections that pass through die to connect different layers of a chip within the same package.

While the language of the TAITRA report was not totally clear, a minimal amount of investigation quickly revealed that the report was comparing apples to oranges, setting up a "race" between Intel's delivery of tri-gate devices with TSMC's offering of chips with TSVs. The only thing that these technologies have in common, essentially, is that they are both technologies that can be described as 3-D, one of the most popular buzzwords in technology these days.

The race between Intel and TSMC imagined by the TAITRA report is not unlike musing about competition between swimmer Michael Phelps and sprinter Usain Bolt at the upcoming 2012 Olympics: two world-class competitors gunning for high-level achievements in completely different sports.

The TAITRA report cited an anonymous source within TSMC saying that TSMC's schedule for 3-D chip rollout matched that of Intel, which has said it expects its tri-gate devices to be ready for volume production by the end of the year. The report did not get into the specifics of the TSMC 3-D technology, instead using language similar to that which Intel used during the tri-gate launch in May to describe 3-D chips in general.

TSMC is developing its own 3-D transistor technology, known as FinFET, which is similar to Intel's tri-gates. But TSMC said as recently as February that it does not expect to put FinFET devices into production until 2015 or 2016. In other words, it's highly unlikely that TAITRA's anonymous TSMC source was referring to TSMC's FinFET technology being in volume production by the end of this year (which would have made it more of an apples to apples comparison).

TSMC has not provided an official production schedule for its TSV technology. In April, TSMC did not provide an update for its TSV roadmap at its annual technology symposium, as the foundry giant has done in the past. TSMC was low key about TSVs this year and said TSV development was "still in the early stages." Nevertheless, it's far more likely that TAITRA's anonymous source was referring to TSV devices being in production by the end of the year than FinFETs. The TAITRA report quoted Shang-Yi Chiang, senior vice president for R&D at TSMC, saying the company has been working closely with packaging and design software providers to commercialize the technology.

Intel, by the way, is also developing 3-D chip stacking through TSVs, as are a host of other semiconductor firms, including Samsung Electronics Co. Ltd., Elpida Memory Inc., IBM Corp., Toshiba Corp. and chip packaging provider Advanced Semiconductor Engineering Inc., among others. It's not yet known when any of these companies plan to put chips with TSVs into production. Last summer, at the International Interconnect Technology Conference, several experts agreed that the technology was some ways away from commercialization.

To sum up: TAITRA circulated a deeply flawed report that falsely equivocated two completely different technologies that have only one thing in common, the fact that they are both described as 3-D technology. Let's assume that this was an honest mistake by TAITRA, based on a fundamental lack of understanding of the technologies. (TAITRA's press agents did not immediately respond to a request for an interview about the creation of the report).

It was a mistake by EE Times (specifically, sloppy journalism by yours truly) to lend credence to the TAITRA report by publishing a story based on it. A good portion of our coverage is based on relevant reports produced by third parties. But journalistic standards demand that we kick the tires of these reports and assess their credibility, and in this case that was not done adequately.


Dylan McGrath

EE Times


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