Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units, and sub-systems for inclusion in full chip designs. Participates in the development of Architecture and Micro-architecture specifications for the Logic components. Provides IP integration support to SoC customers and represents RTL team.


1. Verilog/System Verilog and OVM knowledge.
2. PCIe Architecture knowledge, specifically Gen3.
3. Bachelor of Electronics Engineering.
4. Knowledgeable in pre-silicon design verification using OVM.