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High power consumption has become a major obstacle to further miniature size, semiconductor technology and a serious threat to all in the field of electronic progress 鈹? 鈹? from promoting mobile devices more to the development of super computer miniaturization are included.
Although the fundamental reason lies in the physical and chemical principles of constant, but engineers have developed a series of innovative technology, to reduce the problems facing at present, and future chip industry is expected to revive.
The following discussion of five can be used to reduce the power consumption of the future of IC technology. The technology is now in development, is expected to solve in the next decade will be jointly power consumption problems.
Embrace the collaborative design
Electronic design automation (EDA) tools can make the design team from the start for collaborative design, so as to realize low-power optimization design. In fact, the industry the lowest power consumption of the processor and system level chip developers not only through the optimization of structure and materials to achieve advantage, also USES collaborative design packaging, power supply, radio frequency circuit and the software to reduce the power consumption, without reducing performance or increase the cost.
"Must be employed to achieve low-power technology, design method, the comprehensive method of chip architecture and software." Texas instruments (TI) company design technology and EDA director David Greenhill said.
TI have been used for many advanced technology for each subsystem optimization, thus promoted the new standard for low power components, such as to build their own manufacturing technology to shut off the pattern of the leakage current and active current performance, or the use of voltage and frequency extension technology to define all kinds of working mode to save power.
"The first step from performance and power consumption view to confirm the target of the products. Once the target is determined, you can start using special processing technology, to provide the required performance, while not exceeding equipment power consumption budget." TI 28 nm platform manager Randy Hollingsworth said.
EDA tools has been the key to achieve the lower power consumption, but sometimes need some repeated around the circuit design, because the use of traditional EDA tools for power consumption is estimated to accurate only near the end of the design cycle. For the future of IC, must be conducted at the beginning of the design cycle and accurate power estimation.
Some special tool supplier has picked up the baton. For example, California Atrenta company to launch a called Spyglass Power tools, it can use standard register transfer level (RTL) description to perform the estimated Power consumption, lower Power consumption and validation. The RTL description in the early design cycle can be obtained from each main EDA tools
"Now, engineers hope to earlier in the design cycle of power consumption is estimated." Atrenta senior project director Peter Suaris said, "can't you wait until near the end of the design to estimate the power consumption. You must be in the RTL power consumption for collaborative design, and to design change, so as to achieve energy saving effect from the start."
Atrenta company claims that its special energy saving tools to 20% less than the precision of the estimated final budget, power consumption and power consumption reducing tool also can reduce the power consumption of the final design is up to 50%.
Reduce the working voltage
Miniature chip size can often reduce the working voltage, so as to realize energy saving. Samsung (Samsung), for example, in the latest 20 nm 'green memory chip through will reduce working voltage from 1.5 V to 1.35 V, to save power consumption by 67%.
Processor and logic circuit of the first year of working voltage and even lower than the memory, but when the work voltage is reduced to less than 1 v will inevitably have to further improve the semiconductor processes. IBM, Intel (Intel), samsung, TI, Taiwan semiconductor manufacturing co (TSMC) every semiconductor manufacturers and other continuous improvement process, so that I can work under lower voltage, however, over the past few process speed has started to slow down the progress of the generations.
The key lies in the transistor conduction threshold voltage when using different wafer is not consistent, because in a larger size when the process of change can be ignored. Due to where the fault condition of the leakage current at a particular voltage under different thresholds are very big change, so the ideal chip to use customized power supply voltage according to its characteristics.
Intel claimed to have a better solution 鈹? 鈹? it is the company spent nearly 10 years to complete. Intel has adopted the so-called tri-gate transistors (tri - gate) 3 d FinFET architecture, this architecture in transistor channel in three-dimensional way around three metal gate, the transistor under the electric field of grid. This technology can be offset to stop working voltage is lower than 1 v process changes.
"We have successfully show our tri-gate transistor structure, can be reduced to 0.7 V working voltage range, but also can do less." Intel's senior engineer Mark Bohr says, "these are the more steep the slope of the time threshold completely exhausted transistor, can a small leakage current, faster, cut off at the same time conduction with lower threshold voltage."
Deep-pocketed semiconductor manufacturers to focus on the 3 d simulation of Intel architecture, but some new ventures is committed to research and development of new surface process, in view of the lack of time and money to develop the 3 d semiconductor manufacturers restart voltage adjustment process. SuVolta has already piqued for example have developed a standard CMOS process product line of ultra low voltage plane.
Intelligent control function
In general, when the power supply voltage and pulse rate is lower, the lower the power consumption. However, the performance have also been affected. Therefore, the latest micro controller and SoC sought to use intelligent power management unit, automatic adjust the working voltage and pulse speed to match the workload.
"Power management, the basic idea is to separate different parts site adjust the chip's power supply voltage and pulse rate, so that at any given point in time can match their workload, closing unused circuit at the same time." Incoming Silicon Laboratories, CEO of Tyson said leftovers.
Power management unit is usually in the form of state module build, can selectively reduce the voltage and frequency of the non-critical function. But as semiconductor node becomes more advanced, fill in the chip with more transistors, a so-called "dark field silicon" (dark silicon) concept 鈹? 鈹? the lion's share of the chip power is before you need to use all out 鈹? 鈹? this may is the pioneer of the future semiconductor design concept.
"In the future more advanced process node, such as 22 nm, SoC will be integrated into more transistors can at the same time conduction." Rambus CTO Ely Tsern said, "the concept of dark silicon was produced on a chip the function of many special purpose, but at any given time will only start the function, keep other functions are dark de-energized, doing nothing."
Intel is in the leading position in terms of power management chip, able to monitor the temperature of the core in detail at any time, allowing through ascension frequencies (turbo mode) to improve performance or reduce the speed to save power consumption.
Using 3 d/optical interconnection
Through shortening the length of the interconnect and reduce the wires, the driver can support smaller transistor, and reduces the power consumption of the IC. Shorten the length of the interconnect of the traditional method is to increase the metal layer, so there are some chips metal layer up to 10.
Interconnection layer design, however, the latest innovations is 3 d silicon via (TSV), allows for the storage stack chips on the processor. This technology will reduce the length of the interconnect to the distance between the chip, so don't need a drive transistor and the power consumption of large long PCB interconnect. Economy of the TSV is poorer, however, at present most of the chip maker TSV schedule in the delayed state.
"Although it is true that the silicon via (TSV) can walk through shortening the length of line to reduce the power consumption, but it is a kind of solutions that cost is very high." Greenhill TI company said that "in order to more economical, TSV need to be able to make up for a lack of other (e.g., interface performance), to make it a reasonable cost."
Xilinx (Xilinx nc) is a very understand how to get a balance for the TSV cost/performance of the company, the company is to provide the commercial use of TSV in the first paragraph of the chip. Compared with independent components on the PCB welding way, xilinx adopt the cost-effective solution can not only reduce the power consumption of the chip, and also improves the performance. In addition, it also can reduce the BOM cost for the clients in the xilinx, Ephrem xilinx senior director Wu said.
Xilinx mediation layer through the use of silicon (interposer) avoided the problem of welding on the PCB(This article from:http://pcb.hqew.net/?s=544864) board each FPGA. This si a mediation layer can be in a single package of four high density interconnect the FPGA.
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