Business Title:? Digital Design Engineers for Mixed-Signal Power Management ASICs
Employer: Qualcomm
Qualifications: Design candidates will have a minimum of 2-3 years of relevant experience and must have detailed knowledge of digital ASIC design including architecture, RTL design for control and signal processing functions, linting, synthesis, STA, and DFT. Design candidates must also have experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence. Experience designing mixed signal interfaces and integrating digital modules into mixed-signal ASICs is desirable. Verification candidates should have a minimum of 2-3 years of relevant experience and must have detailed knowledge of self-checking testbench architectures (including directed and random-constrained generation) and coverage-driven verification techniques at the functional, assertion and code levels. Verification candidates will also have a working understanding of Object Oriented System Verilog principles. Experience with VMM, OVM, or UVM is desirable as is experience verifying digital modules in mixed-signal ASICs.
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Hiring location(s):? Singapore

Work Exp: 2 - 3 years
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Roles and Responsibilities: Successful candidates will be responsible for leading, and participating in, the design and verification of leading edge ASICs in advanced digital CMOS processes for multi-function mobile platforms.
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Contact: Qualcomm's online system allows you to create a profile, apply for open positions and track positions youve applied for. https://jobs.qualcomm.com/login/login.xhtml
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