IP Logic Validation Engineers are responsible for the validation & integration of digital logic design blocks. This specific position is for a Senior IP Validation & Integration Engineer in the Hard IP (HIP) WBIO Logic Design team. We are seeking an individual who has a strong working knowledge of high speed I/O Interfaces such as PCIe, SATA, USB2, USB3, SAS, DDR etc. as well as industry verification methodologies & tools to become a key contributor within Hard IP Logic team in developing & validating reusable designs for SoC products across Intel.
The candidate must be able to communicate effectively to senior management, architects, leads and peers. In addition, be self-motivated with the initiative to seek constant improvements in debug and validation methodologies.
The candidate must be able to handle cross-site planning and debug, as well as prioritization of debug activities and resources, as well as the ability to interact effectively with software and hardware engineers.
The candidate must also have strong initiative, self-motivation, analytical/problem solving skills, team working skills, ability to multitask, work within a diverse team and demonstrate good communication skills, attention to detail, and good customer orientation skills as well as critical thinking. Responsibilities include front-end design validation and test failure debug, BFM, testbench & environment development, testplan development, assertion coding, coverage development & analysis, test writing and flow/process automation or enhancements.