As a member of the integration team, he/she would be responsible for the SoC integration process. This includes execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design. Frontend integration tasks include, but not limited to, chip verification, synthesis, netlist generation, static timing analysis and timing closure, formal verification, and design/timing constraint management. In this role, he/she would get to experience many aspects of the SoC design process working as the bridge between RTL designer and the Physical Design designer. He/she would also use/develop various scripts to automate the process where ever possible and work on some of the most complex and highly-integrated chips in the world
? Bachelor degree in Electronic Engineering with 0 - 2 years of relevant experience.
? Good working knowledge of deep submicron SoC integration flow.
? Experience in synthesis and timing closure methodologies and tools (Synopsys Design Compiler and PrimeTime).
? Experience in static timing analysis with OCV.
? Good understanding of top level chip architecture and simulation environment.
? Good understanding of deep submicron issues.
? Good understanding of DFT, Logic BIST and memory BIST.
? Experience in formal verification and tools (Formality / Conformal).
? Proficient in Verilog RTL coding.
? Proficient in Perl, TCL scripting and C/C++ programming.
? Familiar with UNIX/Linux environment.