Job Description
The successful candidate will be responsible for various key tasks in the area of Digital IC design.
The day-to-day tasks for this position include but are not limited to the following:
- Participate in RTL design work.
- Running simulation and debugging failures.
- Supporting the process of integration core IP to SoC.
- Create verification test plan and implement the test bench for design verification
- Implement functional coverage matrix using cover point and assertion
- Review/complete functional and code coverage
The successful candidate will satisfy the following requirements:
- PhD / MSEE / BSEE with up to 2 years relevant experience or equivalent, with concentration in digital design and excellent academic standing
- Preferred to have on-hands experience with VMM/OVM/UVM verification methodology
- Familiar with Hardware description languages (Verilog/SystemVerilog/SystemC), high level languages (C++) and scripting languages (Perl, Tcl)