Xilinx is looking for a system architect to join a fast paced transceiver design team. The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas:
- Channel modelling, IBIS-AMI model development, and system level simulations
- Behavioural modelling of different blocks in transceivers (FFE, CTLE, DFE, CDR, PLL, etc.)
- Adaptive signal processing, coding, and FEC algorithms
- Presenting design trade-off analyses and implementation recommendations with custom circuit designers
The successful applicant should possess:
- MSEE or above
- Hands-on experience in SerDes architecture, IBIS-AMI model development, and high speed serial link system level simulations
- Experience with and good understanding of PLLs, CDRs, equalizers (FFE, CTLE and DFE)
- Familiar with Matlab, Simulink, C/C++, and RTL programming
- Experience with lab equipment for high-speed digital systems
- Good understanding of high speed signal integrity issues
- Excellent technical communication through presentations and documentation
- Ability to collaborate and work well in a team