Job description
- Fully responsible for working in tapeouts of complex designs on various technology nodes and providing valuable suggestion for best implementation.
- Working on several full chip designs both flat and hierarchical and driven the sub-block owners for design closure.
- Interacting with design, verification and DFT teams across all sites of Infineon - Understand and adapt to the current Infineon Implementation flow.
- Working with counterparts in other sites to jointly execute projects as an integral part of the team in global environment.
- Proactively work with expert team to drive improvements in implementation methodology.
- Self-driven and able to work co-operatively with team members to achieve project targets.
- Degree/Masters/PhD in Electrical/Electronic Engineering with more than 4 years of Physical Design Product experience.
- Worked on multiple tape outs at ultra-deep sub-micron technologies, 65nm/40nm and smaller nodes, in complex multi-million gate designs.
- Strong technical knowledge in microelectronics and/or system architectures; experience in Automotive and Industrial domain designs is an advantage.
- Should have hands on experience in front-end RTL to GDSII flow, which includes synthesis, scan insertion, floorplanning, timing closure, timing constraints development, linting, equivalence check etc.,
- Strong experience in timing closure, constraining and timing analysis required.
- Excellent debugging skills to diagnose and devise workarounds for design issues.
- Knowledge on integration of analogue and mixed signal macros.
- Experience in low power/multi voltage design and understanding of UPF is a must.
- Deep knowledge of Synopsys tools and flow is preferred.
- Perl and TCL/TK scripting ability required to achieve highly automated, reproducible and fast results.
- Knowledge about data management tool is a definite plus.