Xilinx is seeking a Design Engineer to join us on a 1 year temporary basis:
- Work on RTL to GDS, including synthesis, placement, clock tree insertion and routing.
- Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
- Work closely with other groups like Design team and layout team to define constraints and integration
- At least a Bachelor's Degree in Electrical/Computer Engineering
- A minimum 3 years of relevant experience
- Good experience and knowledge in design flow from Netlist to GDS, Floor Plan, Synthesis, route, STA, CTS, RC Extraction and correlation
- Static timing analysis, power and noise analysis and back-end verification across multiple projects.
- Proficient with backend design EDA tools Synopsys (preferred) or Cadence
- Successfully track records of taping out complex SOC
- Working knowledge of deep sub-micron routing issues as they relate to power and timing.
- Proficiency using Perl and TCL
- Basic understanding of FPGA architecture
- Basic understanding of how FPGA features will be used by customers
- Good understanding of assigned block functionality