Job Description
- Verilog RTL design
- Integrate different function blocks into Ethernet Switch chip
- Integrate different peripheral into SOC IP
- Integrate IO padring for chip top
- Clock and reset circuit design for chip top
- Run formal tool (formality/verplex)
- Prepare SDC and synthesize RTL design
- Work with DFT team to meet DFT rule
- Work with Physical design team on PnR issue
- Run primetime to check STA result
- Work with package team on ball assignment
- Work with test engineer on ATE vector debugging
-? Assist DV team to debug simulation failure cases
-? Support post-silicon task including chip bring-up, ATE and chip production
-? Develop chip integration document
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Requirements
- Knowledge of Ethernet Switch concepts is a plus.
- Experience with large ASIC project integrations.?
- Understanding of analogue/digital interfaces and techniques.
- With knowledge and skill of IC design flow
- Strong communication skills and willingness to work in a team environment.
- With English communication capability
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https://jobs.broadcom.com/job/Hsinchu-Engineer%2C-Principal-IC-Design-HSQ-300/295792800/