The successful candidate will be responsible for various key tasks in the area of IP verification.
The day-to-day tasks for this position include but are not limited to the following:
- Participate in architecture review and discussion
- Create verification test plan based on architecture specification
- Implement the test bench for design verification
- Implement functional coverage matrix using cover point and assertion
- Review/complete functional and code coverage
- MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing.
- Experience required is typically a BS degree with 9 years of verification experience, or an MS degree with 6 years of verification experience.
- Strong understanding and prior experience of the complete verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production.
- Must have on-hands experience with VMM/OVM/UVM verification methodology and scripting languages (Perl, Tcl).