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Facing the challenges of advanced IC packages

Posted: 01 Sep 1999 ?? ?Print Version ?Bookmark and Share

Keywords:ic package? eda? pcb design? bga? flip chip?

/ARTICLES/1999SEP/1999SEP01_ICD_BD_EDA_ICP_PM_TA.PDF

IC PACKAGING Design Corner 2 Electronics Engineer September 1999 Facing the challenges of advanced IC packages Deep-submicron (DSM) and system- on-a-chip (SoC) trends are placing new demands on the packaging industry. Increased functionality, faster performance, lower operating voltages, reduced size, and increased siliconization have led to increases in die density and I/Os, boosting package pin count and complexity. This, in turn, has created the need for high-density, multi-layer, custom- designed packages such as flip chip, ball-grid-array (BGA), and pin-grid- array (PGA). As a manager of an IC design team today you are aware that your packag- ing engineers are constantly forced to push the boundaries of substrate technologies, assembly yields, and thermal performance. You need a clear understanding of signal-integrity issues, substrate materials and pro- cesses (ceramic, organic, polyimide tape), metallization technologies (thick and thin film, sputtering, conductive foil), and effects on assembly yield (wirebond, wire length and angles, die clearance). Yet, of course, you're asked By Paul Musto Business Manager, High-speed & IC Packaging Technologies Cadence Design Systems This article--the first of two parts--provides guidelines that help IC, package, and board designers and engineers bridge the gap between IC design, package de- sign, package analysis, and board-level issues. Design Corner Manufacturingt echnology rules PCB design library IC-Package-PCBc 0-simulation Package Signal integrity model Signalintegritysimulation 3Dparasiticextraction I/O assignment Wirebound fanout Critical route Automatic route Final cleanup Manufacturing output Die & Package placement Signal integrity analysisP hysical design Advanced IC Packaging Flow High-speedc onstrain derivation & exploration ImportI C Figure 1: In this high-level design flow, the key change is the integration of electrical analysis from the chip through to board design. Techniques for performing simulation at all levels of the design are critical to implementing an effective design environment. 3 Electronics Engineer September 1999 IC PACKAGING Design Corner to design packages that are as inexpen- sive as possible. On top of all this, current package- design methodologies are disjointed. From silicon to package design and analysis to the customers for whom the package is being designed, an environment exists wherein each party is attempting to optimize its own piece independent of the others. On leading-edge designs, this ap- proach breaks down, causing in- creased cycle time due to re-spins or missed design specifications related to performance or cost. However, using new techniques and methodologies, you can now integrate the design process among the disci- plines--improving performance, cost, and cycle times. EDA technology is now emerging that can help solve your complex challenges by creating much-needed links between design, test, and production. This article (the first of two parts) explores in detail the technique of integrating electrical analysis from chip through to board design (figure 1). The process utilized for perform- ing simulation at all levels of the design is crucial to implementing an effective design environment. Chip and package dependencies An IC's input and output interface can greatly affect the success of the end product. The I/O interface can cause the chip to increase in size (which might require a larger, more costly package), generate the requirement for a more sophisticated, custom package design, or drive the need for a reconfigured PCB. You need to address numerous issues throughout the design cycle to minimize or eliminate these effects. At the system level, you will need to define simula- tion and modeling methodologies that allow your chip designers to model the performance of the I/O interface and make the necessary tradeoffs in chip design, package selection/design, and PCB design and layout. These tradeoffs can vary widely. For example, creating tighter, stag- gered I/O pad pitches can lead to denser wirebond patterns with potentially longer wires. In other cases, the die may be bumped to a flip-chip array pattern. Longer wirebonds increase inductance, a main cause of signal noise--a signifi- cant problem in today's high-end chips. In the case of the flip chip, line inductance and switching noise are reduced, but interconnect length for I/O redistribution is increased, causing additional delay. While the actual delay time may be insignifi- cant, the associated cost and reliabil- ity issues may be prohibiting factors. To manage these challenges, silicon designers must invest in simulations, taking into account the detailed parasitics of the chip and package together with the system require- ments. This helps to model antici- pated performance and induce tradeoffs. Interspersing of I/O buffers, taking advantage of non-switching buffer groups, and distributing power and grounds around the device are all done today, but with much difficulty and, often, months worth of effort. A chip/package I/O planner's basic requirements include a tool that requires minimal knowledge of package design to use, has a consis- tent use model with the IC environ- ment, and has easy and quick access to package models from either the ASIC or package foundry. A devel- oped package model would then be imported into the design system as a simple bondfinger layout, power/gnd structure, and cavity outline. The rest of the package would be modeled only through Spice-based parasitic models to be used for electrical simulation. Design for manufacturability The functional blocks and I/O padring of the chip are determined during the chip floorplanning phase. With an integrated methodology, the silicon designer can use the package model to assign the signal and power/ground What's Online Making the connection with wire bonding www.ee.asiansources.com/article_ content.php3?article_id=8800013084 Advanced ICs drive post-fab changes www.ee.asiansources.com/article_ content.php3?article_id=8800010223 Processing advanced bare die assemblies www.ee.asiansources.com/article_ content.php3?article_id=8800012383 Design PCBs to use BGA packages www.ee.asiansources.com/article_ content.php3?article_id=8800009897 Flip chip underfill increases thermal reliability www.ee.asiansources.com/article_ content.php3?article_id=8800009823 www.ee.asiansources.com Figure 2: This photograph shows a package design database that has been automatically transferred into a 3D parasitic extraction tool. The parasitic extraction tool produces 3D resistance, inductance, capacitance, and conductance (RLCG) values and is used for more accurate signal-integrity analysis. IC PACKAGING Design Corner 4 Electronics Engineer September 1999 I/Os to either bondfingers or a power or ground ring. (In a case where the package has internal power/ground, the connection would be defined through a bondfinger.) The silicon designer can now check for manufacturability and/or simulate for electrical performance. Manufacturability checks are physical design rules to determine whether the package type chosen is a viable option. These checks include wirebond minimum and maximum length, wire-to-wire spacing, maxi- mum wire angle, cavity-edge clear- ance, and sufficient bondfinger locations to supply all of the chip I/Os. For performance analysis, the parasitic models would include the interconnect within the package and potential board-loading information. The analysis and tradeoffs can focus on overall signal performance optimi- zation, through parameters such as signal-to-reference ratios and buffer strength optimization, or on switch- ing-noise reduction. For example, to reduce switching noise or noise on quiet lines, the designer might insert extra power and ground I/Os. These extra I/Os may increase the chip's size, which would limit the packaging options. Instead, the designer may choose to investi- gate other alternatives, such as interleaving non-switching buffers, modifying buffers, or modifying the timing. The designer may also want to analyze the effects of using a pack- age that offers internal power and ground substrate layers versus a power-and-ground ring on the surface of the package. All of these scenarios require knowledge of various packages' physical and electrical characteristics. To make this environment and methodology a reality, chip designers need access to package models. This means that package foundries must begin supplying package data to their ASIC customers for distribution and, in turn, that the ASIC foundry and supplier work closely so that require- ments are clear. This is beginning to happen with many of the larger semiconductor houses and will provide a foundation for others to adopt this solution. Measuring package signal integrity Package signal integrity is becoming more of a challenge in high-speed IC Process step Define DIE Define Package Define Board load ? Establish Buffer-to-DiePad connectivity (Pin/Pad assignment) ? Establish connectivity of PWR/GND network to DiePads and Buffers ?EstablishDietoPackageConnectivity(Drawwiresorconnectbristles) ?EstablishPkgtoBoardConnectivity(Matchnet_namesorconnectbristles) ReadtoStartSimulating/What-If! ? Read in DIE format ? Create DIE through spreadsheet ? Read in IC design ? Read in design ? Read in PDF file ? Create Pkg through "PKG generator" ? Read in Clip files or Create PWR/GND rings ? Read in electrical model (BrdModel, LPM, Package Model) ? Create scratch electrical model ?ReadinBrdModel ?ReadinSpice interconnectmodel ?Createinterconnect modelonthefly ?Terminateinlumped passivesorActive RCVRs(Spice,IBIS, SigNoise,BSIM3,etc.) ? Read in buffer (Spice, IBIS, SigNoise, BSIM3, SE cell) ? Read in PWR/GND network (SPICE/SE?) or create a defaultL PWR/GND network Physical environment Electrical environment Figure 3: This flowchart illustrates the design flow employed by signal-integrity engineers, as well as the steps that can be saved through the use of an integrated process. 5 Electronics Engineer September 1999 IC PACKAGING Design Corner You may e-mail your comments on thisYou may e-mail your comments on thisYou may e-mail your comments on thisYou may e-mail your comments on thisYou may e-mail your comments on this article to Paul Musto at psm@article to Paul Musto at psm@article to Paul Musto at psm@article to Paul Musto at psm@article to Paul Musto at psm@ cadence.com; or fax: 1-978-2626777.cadence.com; or fax: 1-978-2626777.cadence.com; or fax: 1-978-2626777.cadence.com; or fax: 1-978-2626777.cadence.com; or fax: 1-978-2626777. packages. Unfortunately, the methods that are used today are not well integrated into the package design process and are reserved for the "expert" analysts. These analysts use sophisticated techniques to solve complex problems, but the results rarely affect the actual design. In most instances, analysis is performed after the package design is com- pleted. The engineer then takes some characteristics about the design and some critical net information and attempts to recreate the data within his or her local modeling software. This process alone can take upwards of two weeks. Once the data is physically mod- eled, the parasitics can then be generated and simulations per- formed. If problems are detected at this point, the designer can modify the package, delaying the project, or work around it at the board level. Since overall system constraints are becoming far more complex (tighter and denser), the latter option can be extremely limited, creating poten- tially severe problems downstream. Today's methodology requires a tool that allows the signal-integrity engineer to explore pre-layout options, design signal and power/ ground plane distribution require- ments, implement them in physical design, and then perform concurrent validation with layout. This method- ology would reduce the design cycle time up to 75 percent for high-speed devices and also provide cost and performance improvements to downstream system designs. This is a great goal, but is it realis- tic? If so, what are the barriers? The first answer is "Yes". Tools are available that can assist an engineer throughout the exploration, design, implementation, and validation phases. Where complications arise depends on the accuracy of the core engines that these tools use. Cur- rently, most of the tools use a 2D+ field-solver engine. These engines begin to lose accuracy when modeling 3D elements such as non-parallel traces, wirebonds, bumps, ball, etc. The tools that are inherently used by the engineer in today's environments have 3D solving capabilities that handle these geometries. The problem with these tools is that they are typically difficult to use, have no intelligent integration with design or interactive capabilities, and take a long time to solve problems. Clearly, the barrier here is that the two environments need to be inte- grated and their inherent deficiencies solved. One solution is recent partnerships between CAD tool vendors aimed at creating a tightly integrated physical and electrical solution that lets the engineer quickly create or modify geometries and then automatically extract the accurate 3D parasitics. Figure 2 provides a graphic representation of such improved 3D signal-integrity analysis, while figure 3 offers an overview of the design flow used by the signal- integrity package engineer. Within this environment, the engineer does not need to be bur- dened with too much detail about the physical layout. Tools exist that allow engineers to quickly create package substrate stack-ups and die footprints, assign logic, and route without having to be physical CAD engineers. With limited design information, the engineer can model topologies of critical net interconnect and simulate them against his or her desired results. The end goal for the engineer during this phase is to define con- straints that will govern the physical layout of critical paths and the power/ ground distribution of the package. The constraints for interconnect routing can be defined in terms of delay, crosstalk, impedance, and/or inductance. The downstream physical layout tool must be capable of implementing these constraints to ensure design intent. For layout, a 2D+ analysis solution provides a quick and "accurate enough" calculation to weed out the vast majority of problems. During this process, the engineer has con- tinual access to the design to perform a more accurate 3D analysis of critical nets. Because electrical constraints have been implemented and checked throughout layout, the modifications required should be minimal. This tight integration of a 3D parasitic engine allows for quick and easy validation of electrical performance. Upon completion, the engineer performs final verification of the package. Since rules have been defined, checked, and validated throughout the entire process, the issues uncovered should be minimal and resolvable before being sent to manufacturing. The final task performed by the engineer is the generation of a partial or complete parasitic model for the package to be used within the PCB analysis envi- ronment. These models will greatly improve simulation accuracy of system-level interconnect. Most board signal-integrity tools can utilize the I/O Buffer Informa- tion Specification (IBIS), which is used for defining I/O buffer charac- teristics. However, IBIS has limita- tions for package modeling. For a more accurate representation, generic Spice models could be generated, but the most efficient format would be the one used by the board signal- integrity tool, which is typically Spice-based. Part II of this article--focusing on physical design issues relevant to advanced IC packaging--will appear in next month's issue.




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