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Facing the challenges of advanced IC packages

Posted: 01 Oct 1999 ?? ?Print Version ?Bookmark and Share

Keywords:ic package? eda? pcb design? bga? flip chip?

/ARTICLES/1999OCT/1999OCT01_ICD_BD_EDA_ICP_PM_TA.PDF

IC PACKAGING Design Corner 2 Electronics Engineer October 1999 Facing the challenges of advanced IC packages Deep-submicron (DSM) and system-on-a-chip (SoC) trends are placing new demands on the packaging industry. Increased functionality, faster performance, lower operating voltages, reduced size, and increased siliconization have led to increases in die density and input/outputs (I/Os), boosting package pin count and complexity. This, in turn, has created the need for high-density, multi-layer, custom-designed packages such as flip chip, BGA, and pin-grid- array (PGA). The first article in this two-part series showed how current package- design methodologies are disjointed. On leading-edge designs, this approach breaks down, causing increased cycle time due to re-spins or missed design specifications related to performance or cost. This article describes new tech- niques and methodologies that you can now use to integrate the design process among the disciplines-- improving performance, cost, and cycle times. EDA technology is now emerging that can help solve your complex challenges by creating much-needed links between design, test, and production. Physical design overview Over the past year, many companies have adopted EDA tools for physical layout. This development has been driven by the fast-growing BGA package market, as well as compa- nies' realization that old design tools, mostly mechanical, were limiting the ability to design complex substrates. Figure 1 shows an example of the output that you can attain through automated tool capabilities. This article--the second of a two-part series-- provides guidelines that help IC, package, and board designers and engineers bridge the gap between IC design, pack- age design, package analysis, and board-level issues. By Paul Musto Business Manager, High-speed & IC Packaging Technologies Cadence Design Systems Design Corner Figure 1Figure 1Figure 1Figure 1Figure 1: Today's designs have high pin-count die and package substrates and require many angle routing, arc-radial wirebonding, and complex power and ground structures. Automated design tools will reduce cycle time and help you accomplish these tasks. Figure 2Figure 2Figure 2Figure 2Figure 2: Shown here are a package design, a board design with the corresponding package, and an extracted signal topology. You can extract topologies and make analysis tradeoffs with a simple click of a button. IC PACKAGING Design Corner 3 Electronics Engineer October 1999 Utilizing these newer EDA tools and methodologies, many companies have achieved substantial reductions in cycle time. The biggest challenge the design community has faced is transitioning from a mechanical, non-intelligent methodology to a tool that provides on-line design rule checking and automation, at the expense of some complexity. How- ever, the original flow does not change, and the new solution is far more efficient. The beginning phases of the package design focus on creation of the die, substrate, and plating bar, if needed. Initially, you do not require a netlist for the die-to-package intercon- nect. You can create the netlist later, determined by the location of the die I/O, bondfingers, and the package I/Os. This set-up process should be straightforward and take only a short time to complete. One area in which these tools can benefit you is the early phases of design, by automating the creation of the die, package, and plating-bar footprints. Another key advantage afforded by EDA tools is the ability to model and check complex structures against a detailed set of rules, or constraints. These constraints, which ensure that the design meets manufac- turing and electrical specifications, fall into two categories: physical and electrical. Electrical and physical constraints Electrical constraints are delay and distortion specifications for critical nets. Physical constraints are me- chanical design guidelines to ensure manufacturability. The design system helps you check against these con- straints automatically throughout the entire design process. The stack-up information is the definition of all the manufacturable layers in the substrate. This includes conductive layers, dielectric layers, paste layers, and shield planes. The information needed to complete an accurate stack-up includes material type, layer type, name, thickness, dielectric constant, and electrical conductivity. You can use this infor- mation to check both physical and electrical constraints. Once com- pleted, you can then capture the stack- up and constraint information as a technology file, which you can then reuse on other designs to reduce setup effort and time. If your design uses wirebond interconnect (still the predominant method), the configurations will vary from in-line or in-line radial, to multi- tiered, arc-based patterns. The package technology and the density of chip I/Os will determine the type of pattern used. Once you've established the configuration and pattern, you can employ other guiding constraints, including: ? bondfinger dimension, ? bondfinger spacings, ? minimum and maximum wire length, ? maximum bondwire angle (only for radial), and ? number of rows in stagger or shelves, if applicable. Using these constraints, the system can automatically generate a pattern that meets all conditions. If special bondfinger shapes or locations are necessary, then you have the option to use interactive utilities. At this point, the only logic typi- cally contained in the design database is that of the die. Using automatic and interactive assignment utilities, you can optimize routability and electrical performance. The first step in defin- ing the pin assignment is to determine the package I/Os that will provide power and ground. Most companies will have a pre-assigned set of pins that can be either fed in through the use of a netlist format or, if such a format is not available, manually assigned. This is also the point at What's Online Making the connection with wire bonding www.ee.asiansources.com/article_ content.php3?article_id=8800013084 Advanced ICs drive post-fab changes www.ee.asiansources.com/article_ content.php3?article_id=8800010223 Processing advanced bare die assemblies www.ee.asiansources.com/article_ content.php3?article_id=8800012383 Design PCBs to use BGA packages www.ee.asiansources.com/article_ content.php3?article_id=8800009897 www.ee.asiansources.com which you should determine and pre- assign critical signals. You can then use the remaining package pins for full automatic signal assignment. If a plating bar exists, you can also now use the assignment utility to build the package I/O to plating bar connectiv- ity. This connectivity will drive automatic and interactive routing. You can use signal integrity and timing analysis at this point to detect problems based on Manhattan-length values. You may also use this infor- mation to correct issues before time and effort has been invested in routing. It is costly and time-consum- ing to address these issues later on in the design cycle. At this stage, it may also be useful to show the design to the signal-integrity engineer for 3D parasitic extraction of the wires. Routing is the most time-consuming phase. It is critical that engineering and manufacturing intent are captured fully to meet product specifications. Depending on the technology being implemented, this routing may take on different formations, from an orthogonal to a dense, all-angle IC PACKAGING Design Corner 4 Electronics Engineer October 1999 routing. All of these routing patterns are the result of an optimized usage of routing real estate, resulting in the minimum number of needed layers. Over the past year, EDA companies have introduced new autorouters to handle package routing. These tools can be extremely effective but will also need good interactive routing to complete the job. One technique being used is to have a router perform the route using orthogonal and diagonal methods and then have special routines "stretch and smooth" the routes to any angle. These tech- niques have been effective to help achieve high completion rates in a very short time. It is also critical to take advantage of constraint-driven routing for delay- and distortion- based rules, such as delay and crosstalk. Adherence to these rules during routing will sift out most of any potential signal-integrity issues, thus minimizing rework after detailed analysis is performed. Next, you can quickly scan the entire design and compare it against the electrical constraints to identify the signals that are marginal or failing. Once again, make sure you notify the signal-integrity engineer that the design is available for de- tailed analysis. You should correct any issues found in either the scan- ning or detailed verification process at this point. Before preparing the design for manufacturing, you must perform pad filleting, line smoothing, and final cleanup. Manufacturing preparation and output generation comprise the final phase of package design. This phase will vary, depending on which foundry you use and your own internal requirements for documentation. However, you will need to accomplish two main tasks: documentation drawings and manufacturing output. Due to focus from the EDA industry to develop foundry relationships, your foundry may already own a commer- cial tool. In these instances, foundries may simply accept the ECAD design database as manufacturing input. The foundry can use the database to enhance manufacturing yields and implement any last minute changes to the package. If you intend to use this process for manufacturing, it is imperative that you first consult with your company to determine if you must modify or remove any informa- tion from the database. This will ensure that intellectual property is retained only within your company. System-level hand-off You should adopt the same approach (used for passing data from the IC environment to package design) when you are preparing to pass component- level information to the system-design group for use in board-level floorplanning, analysis, and layout. Valuable information transferred at this stage includes: ? Physical footprint, ? Schematic footprint, ? I/O buffer models, and ? Package models, either in Spice, IBIS, or proprietary format. For the PCB designer, this method- ology enables simulation and design that includes more than just a "black- box" component. The output of a complete library reduces the set-up time and increases data accuracy. In high-performance designs, package parasitics can mean the difference between a working and a non-working board. In most cases today, the models being used by board-level design engineers contain only the I/O buffer characteristics and do not include package parasitics. In some cases, these package parasitics can cause adverse effects to active and inactive I/O signals. Utilizing package models within board simulation provides an accurate picture of the total signal quality. If there is a common design system between package and board, you can create a hierarchical simulation environment with which you can simulate the interconnect right from the chip I/O, through the wirebond, package, package pin, board, and into a receiving load (figure 2). Tradeoffs and conclusions Leading-edge product designs con- tinue to push the limits of chip performance, size, and cost, which, in turn, affect the package and, eventu- ally, the end system. Tradeoffs are necessary, and often their implications are not fully understood until late in production. Product changes late in the development cycle are costly in terms of market opportunity, as well as the obvious schedule and budget overruns. Having an integrated and streamlined methodology that takes into consideration the chip, package, and board will reduce these problems. Until now, design communities did not realize that EDA suppliers offer solutions that can address these challenges. However, they represent a complete methodology shift that reaches beyond group, division, and, in many instances, company bound- aries. Implementing these solutions requires a shift in the way the elec- tronics industry approaches the design of its products. It takes strong com- munication and a belief that suppliers are not only producers of goods but are your partners. These "partners" should be ready and willing to provide data that helps leverage your strengths while enhancing their own ability to succeed in a competitive market. The first part of this article appeared in the September 1999 issue. You can also download a copy of the article at www.ee.asiansources.com/article_ content.php3?article_ id=8800015883. You may e-mail your comments on thisYou may e-mail your comments on thisYou may e-mail your comments on thisYou may e-mail your comments on thisYou may e-mail your comments on this article to Paul Musto at psm@cadence.article to Paul Musto at psm@cadence.article to Paul Musto at psm@cadence.article to Paul Musto at psm@cadence.article to Paul Musto at psm@cadence. com; or fax: 1-978-2626777.com; or fax: 1-978-2626777.com; or fax: 1-978-2626777.com; or fax: 1-978-2626777.com; or fax: 1-978-2626777.




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