Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > FPGAs/PLDs
?
?
FPGAs/PLDs??

Are your PLDs metastable?

Posted: 08 Oct 1999 ?? ?Print Version ?Bookmark and Share

Keywords:programmable logic? pld? metastable? logic? digital circuits?

/ARTICLES/1999OCT/1999OCT08_PL_AN.PDF

fax id: 6403 Cypress Semiconductor Corporation ? 3901 North First Street ? San Jose ? CA 95134 ? 408-943-2600 May 1992 - Revised March 6, 1997 Are Your PLDs Metastable? This application note provides a detailed description of the metastable behavior in PLDs from both circuit and statistical viewpoints. Additionally, the information on the metastable characteristics of Cypress PLDs presented here can help you achieve any desired degree of reliability. Metastable is a Greek word meaning "in between." Metasta- bility is an undesirable output condition of digital logic storage elements caused by marginal triggering. This marginal trig- gering is usually caused by violating the storage elements' minimum set-up and hold times. In most logic families, metastability is seen as a voltage level in the area between a logic HIGH and a logic LOW. Although systems have been designed that did not account for meta- stability, its effects have taken their toll on many of those sys- tems. In most digital systems, marginal triggering of storage ele- ments does not occur. These systems are designed as syn- chronous systems that meet or exceed their components' worst-case specifications. Totally synchronous design is not possible for systems that impose no fixed relationship be- tween input signals and the local system clock. This includes systems with asynchronous bus arbitration, telecommunica- tions equipment, and most I/O interfaces. For these systems to function properly, it is necessary to synchronize the incom- ing asynchronous signals with the local system clock before using them. Figure 1 shows a simple synchronizer, whose asynchronous input comes from outside the local system. The synchronizer operates with a system clock that is synchronous to the local system's operation. On each rising edge of this system clock, the synchronizer attempts to capture the state of the asyn- chronous input. Figure 2 shows the expected result. Most of the time, this synchronizer performs as desired. Digital systems are supposed to function properly all the time, however. But because there is no direct relationship between the asynchronous input and the system clock, at some point the two signals will both be in transition at very nearly the same instant. Figure 3 shows some of the synchronizer's possible metastable outputs when this input condition occurs. These types of outputs would not occur if the synchronizer made a decision one way or the other in its specified clock-to-output time. A flip-flop, when not properly triggered, might not make a decision in this time. When improperly trig- gered into a metastable state, the output might later transition to a HIGH or a LOW or might oscillate. When other components in the local system sample the syn- chronizer's metastable output, they might also become meta- stable. A potentially worse problem can occur if two or more components sample the metastable signal and yield different results. This situation can easily corrupt data or cause a sys- tem failure. Such system failures are not a new problem. In 1952, Lubkin (Reference 1) stated that system designers, including the de- signers of the ENIAC, knew about metastability. The accept- ed solution at that time was to concatenate an additional flip-flop after the original synchronizer stage (Figure 4). This added flip-flop does not totally remove the problem but does improve reliability. This same solution is still in wide use today. Figure 1. Simple Synchronizer Figure 2. Expected Synchronizer Output LOCALLY SYNCHRONOUS OUTPUT Q D SYNCHRONIZERASYNCHRONOUS INPUT SYSTEM CLOCK SYNCHRONOUS SYSTEM CLOCK ASYNC INPUT SYNCH OUTPUT Figure 3. Possible Metastable States of Synchronizer Figure 4. Two-Stage Synchronizer CLOCK ASYNC INPUT METASTABLE OSCILLATING OUTPUT METASTABLE RESOLVE TO 1 METASTABLE RESOLVE TO 0 SYNC OUT LOCALLY Q D SYNC_OUT Q D INTERMEDIATE SIGNALASYNC_IN CLOCK SYNCHRONIZER SYNCHRONOUS SYSTEM Are Your PLDs Metastable? 2 Recovery from metastability is probabilistic. In the improved synchronizer, the first flip-flop's output might still be in a meta- stable state at the end of the sample clock period. Because the flip-flops are sequential, the probability of propagating a metastable condition from the second flip-flop stage is the square of the probability of the first flip-flop remaining meta- stable for its sample clock period. This type of synchronizer does have the drawback of adding one clock cycle of latency, which might be unacceptable in some systems. As system speeds increase and as more systems utilize in- puts from asynchronous external sources, metastability-in- duced failures become an increasingly significant portion of the total possible system failures. So far, no known method totally eliminates the possibility of metastability. However, while you cannot eliminate metastability, you can employ de- sign techniques that make its probability relatively small com- pared with other failure modes. Explanation of Metastability In a flip-flop, a metastable output is undefined or oscillates between HIGH and LOW for an indefinite time due to margin- al triggering of the circuit. This anomalous flip-flop behavior results when data inputs violate the specified set-up and hold times with respect to the clock. In the case of a D-type flip-flop, the data must be stable at the device's D input before the clock edge by a time known as the set-up time, ts. This data must remain stable after the clock edge by a time known as the hold time, th (Figure 5). The data signal must satisfy both the set-up and hold times to ensure that the storage device (register, flip-flop, latch) stores valid data and to ensure that the outputs present valid data after a maximum specified clock-to-output delay tco_max. As used in this application note, tco_max refers to the interval from the clock's rising edge to the time the data is valid on the outputs. In most cases, tco_max refers to the maximum tco specified by a data sheet, as opposed to the average or typical tco value. If the data violates either the set-up or hold specifications, the flip-flop output might go to an anomalous state for a time greater than tco_max (Figure 5). The additional time it takes the outputs to reach a valid level can range from a few hun- dred picoseconds to tens of microseconds. The amount of additional time beyond tco_max required for the outputs to reach a valid logic level is known as the metastable walk-out time. This walk-out time, while statistically predictable, is not deterministic. Figure 6, from Reference 2, shows the variation in output de- lay with data input time. The left portion of the graph shows that when the data meets the required set-up time, the device has valid output after a predictable delay, which equals tco. The middle portion of the graph indicates the metastable re- gion. If the data transitions in this region, valid output is de- layed beyond tco_max. The closer the input transitions to the center of the metastable region, violating the device's trigger- ing requirements, the longer the propagation delay. If the data transitions after the metastable region, the device does not recognize the input at that clock edge, and no transition oc- curs at the output. As given in Reference, you can predict the region tw, where data transitions cause a propagation delay longer than t, from the formula: Eq. 1 where t depends on device-specific characteristics such as transistor dimensions and the flip-flop's gain-bandwidth prod- uct. Figure 7 shows another way of looking at metastability. A flip-flop, like any other bistable device, has two minimum-po- tential energy levels, separated by a maximum-energy poten- tial. A bistable system has stability at either of the two mini- mum-energy points. The system can also have temporary stability--metastability--at the energy maximum. If nothing pushes the system from the maximum-energy point, the sys- tem remains at this point indefinitely. Figure 5. Triggering Modes of a Simple Flip-Flop CLOCK INPUT OUTPUT ts > ts_max th > th_max ts tco_max Figure 6. Output Propagation vs. Data Transition Figure 7. Triggering Modes of a Simple Flip-Flop tw tcoe t tco?( )? ---------------------- = Are Your PLDs Metastable? 3 A hill with valleys on either side is another bistable system. A ball placed on top of the hill tends to roll toward one of the minimum-energy levels. If left undisturbed at the top, the ball can remain there for an indeterminate amount of time. As this figure indicates, the characteristics of the top of the hill as well as natural factors affect how long the ball stays there. The steepness of the hill is analogous to the gain-bandwidth prod- uct of the flip-flop's input stage. Causes of Metastability Systems with separate entities, each running at different clock rates, are called globally asynchronous systems (Ref- erence 4). The entities might include keyboards, communica- tion devices, disk drives, and processors. A system contain- ing such entities is asynchronous because signals between two or more entities do not share a fixed relationship. Metastability can occur between two concurrently operating digital systems that lack a common time reference. For exam- ple, in a multiprocessing system, it is possible that a request for data from one system can occur at nearly the exact mo- ment that this signal is sampled by another part of the system. In this case, the request might be undefined if it does not obey the set-up and hold time of the requested system. When globally asynchronous systems communicate with each other, their signals must be synchronized. Arbitration must occur when two or more requests for a shared resource are received from asynchronous systems. An arbiter decides which of two events should be serviced first. A synchronizer, which is a type of arbiter with a clock as one of the arbited signals, must make its decision within a fixed amount of time. A device can synchronize an input signal from an external, asynchronous device in cases such as a keyboard input, an external interrupt, or a communication request. Care must be taken when two locally synchronous systems communicate in a globally asynchronous environment. A syn- chronization failure occurs when one system samples a flip-flop in the other system that has an undefined or oscillat- ing output. This event can distribute non-binary signals through a binary system (Reference 5). In synchronizers, the circuit must decide the state of the data input at the clock input's rising edge. If these two signals ar- rive at the same time, the circuit can produce an output based on either decision, but must decide one way or the other with- in a fixed amount of time. Attacking Metastability The design of synchronous systems is much different than the design of globally asynchronous systems. The design of a synchronous digital system is based on known maximum propagation delays of flip-flops and logical gates. Asynchro- nous systems by definition have no fixed relationship with each other, and therefore, any propagation delay from one locally synchronous system to the next has no physical mean- ing. Two different methods are available to produce locally syn- chronous systems from globally asynchronous systems. The first method involves creating self-timed systems. In a self-timed system, the entity that performs a task also emits a signal that indicates the task's completion. This handshak- ing signal allows the use of the results when they are ready instead of waiting for the worst-case delay. Such handshaking signals allow communications between locally synchronous systems. The advantage of the self-timed method is that it permits ma- chines to run at the average speed instead of the worst-case speed. The disadvantages are that a self-timed system must have extra circuitry to compute its own completion signals and extra circuitry to check for the completion of any tasks assigned to external entities. Petri Nets, data flow machines, and self-timed modules all use the self-timed method of communication among locally synchronous systems. Self-timed structures do not complete- ly eliminate metastability, however, because they can include arbiters that can be metastable. Most systems do not include self-timed interfaces due to the additional circuitry and com- plexity. The second method of producing locally synchronous sys- tems from globally asynchronous systems is the simple syn- chronizer. This is the most common way of communicating between asynchronous objects. The metastability errors that might arise from these systems must be made to play an in- significant role when compared with other causes of system failure. Many metastability solutions involve special circuits (Refer- ences 6 and 7). Some of these solutions do not reduce meta- stability at all (References 13 and 8). Others, however, do reduce metastability errors by pushing the occurrence of metastability to a place where sufficient time is available for resolving the error. Most of these circuits are system depen- dent and do not offer a universal solution to metastability er- rors. The easiest and the most widely used solution is to give the synchronizing circuit enough time to both synchronize the sig- nal and resolve any possible metastable event before other parts of the system sample the synchronized output. This so- lution requires knowledge of the metastable characteristics of the device performing the synchronization. Many semiconductor companies have developed circuits such as arbiters, flip-flops, and latches that are specifically designed to reduce the occurrence of metastability. Although these parts might have good metastability characteristics, they have very limited application. The circuits can only func- tion as flip-flops or arbiters and do not have the flexibility of PLDs. Cypress Semiconductor has designed the flip-flops in the company's PLDs to be metastability hardened. This al- lows you to use Cypress PLDs in a wide range of systems requiring synchronization. Circuit Analysis of Metastability Many authors have written papers detailing the analysis of metastability from a circuit standpoint (References 5, 7, 8, 9, 10, 11, and 12). In Reference 11, for example, Kacprzak pre- sents a detailed analysis of an RS flip-flop's metastable oper- ation. He states that a flip-flop has two stages of metastable operation (Figure 8). During the initialization phase, the Q and Q outputs move simultaneously from their existing levels to the metastable voltage Vm, which is the voltage at which Vq = Vq. The second or resolving phase occurs when the outputs once again drift toward stable voltages. Once a flip-flop has en- tered a metastable state, the device can stay there for an indeterminate length of time. The probability that the flip-flop Are Your PLDs Metastable? 4 will stay metastable for an unusually long period of time is zero, however, due to factors such as noise, temperature im- balance within the chip, transistor differences, and variance in input timing. During the second phase of metastability, for very small deviations around the metastable voltage, Vm, the flip-flop behaves like two cross-coupled linear amplifier stag- es that gain Vd = Vq ? Vq. When the gain of the cross-coupled loop exceeds unity, the differential voltage increases expo- nentially with time. The length of time the flip-flop takes to resolve cannot be exactly determined. The probability that the flip-flop will re- solve within a specific length of time, however, can be predict- ed. This probability depends on the electrical parameters of the flip-flop acting as a linear amplifier around the metastabil- ity voltage. The solution (Reference 11) to the differential volt- age Vd(t) driving the resolving phase is given by Eq. 2 where t depends directly on the amplifier gain and capaci- tance, and where Vd(t0) represents the differential voltage at some time t0. You can use this equation to determine the length of time that the output voltage will take to drift from the metastable voltage Vm to a specified voltage difference Vd. Horstmann (Reference 5) states that a flip-flop, like any other system with two stable states, can be described by an energy function with two local energy minima where P(x) = 0 (Figure 9). Any bistable system has at least one metastable state, which is an unstable energy level within the system and rep- resents the local maximum of the energy function. The sys- tem's gradient can be represented by a force, F(x), that is zero at stable and metastable states (inflection points of the energy function). Figure 10 shows a simplified first-order model of an RS flip-flop used to predict and visualize metastability. A flip-flop energy transfer curve (Figure 11) shows the relationship be- tween the two outputs. The two stable states are local energy minima of the system. The metastable state, M, is a local energy maximum and represents an unstable state with loop gain near M that is greater than one. Figure 12 shows the trigger line for the first-order approxima- tion of the flip-flop. The dashed line RS represents the de- vice's normal trigger line, which does not follow the transfer curve because, during triggering, the feedback loop has not been established. If at varying points along the trigger line the feedback loop is re-established, the nodes of the device fol- low the curves that lead to the line S0 ? S1. Once on this line, the circuit exponentially drifts toward stability at either S0 or S1, depending on which side of the line Q = Q the feedback loop was re-established. The curves are solutions to the Figure 8. Two Phases of Metastability Vd t( ) Vd t0( )e t t0?( ) ---------------- = Figure 9. Energy/Force Function of a Bistable System Figure 10. First-Order Flip-Flop Figure 11. Energy Transfer Diagram of Simple RS Flip-Flop S Vin1 V o Q V o Q Vin2 R Are Your PLDs Metastable? 5 first-order model circuit equations for the device shown in Fig- ure 10. When the feedback loop is restored near the line Q = Q, the system moves toward the unstable state M and can take an indefinite amount of time to exit from this metastable state. You can see this from the graph by noticing that S0 and S1 are equally likely solutions for system stability from M. Once the feedback loop is re-established, the system exponentially de- cays toward M and then exponentially grows toward S0 or S1. Figure 13 shows the system's possible trigger events using the implied time scale of the state-space curves. The solution of these simplified first-order equations indicates that the fast- est metastable resolution time occurs when the circuit's gain-bandwidth product is maximized. Flannagan (Reference 12), in an attempt to maximize the gain-bandwidth product, solves simplified flip-flop equations to determine the phase trajectory near the metastable point. His results, which are supported by other authors, indicate that p and n devices with equal geometries produce the opti- mal gain-bandwidth product for metastable event resolution. Statistical Analysis of Metastability To begin the analysis of metastability, assume that the flip-flop's probability of resolving its metastable state does not depend on its previous metastable state. In other words, the metastable device has no memory of how long it has been in a metastable region. The analysis of metastability also as- sumes that the flip-flop's probability of resolving its metasta- ble state in a given time interval does not depend on the meta- stable resolution in another disjoint time interval. The probability that a metastable event will resolve in a given in- terval (0,t) is only proportional to the length of the interval. These assumptions yield an exponential distribution that de- scribes the probability that the flip-flop resolves its metasta- bility at a time t. The exponential distribution has the form Eq. 3 where m is the expected value of metastability resolution per unit time (settling rate). Using this equation and given that the flip-flop was metasta- ble at time t = 0, the probability of a metastable event lasting a time t or longer is Eq. 4 The next part of the analysis involves the probability that the flip-flop is metastable at time t = 0. This part of the analysis assumes that the probability that the data transitions in a giv- en time interval depends only on the length of the interval. A Poisson process with rate fd describes the probability of the data transitioning at a time t: Eq. 5 where x is the number of transitions. If a data transition within a bounded time interval, W, of the clock edge causes a metastable condition, the expected number of transitions of this Poisson process with rate fd in time interval W is Eq. 6 Because this expected number of transitions is the same as the probability that the flip-flop is metastable at t = 0, the equa- tion for the probability at t = 0 is Eq. 7 Using Equations 5 and 7, the probability that a given clock cycle results in metastability that lasts at most a time t is Eq. 8 Figure 12. Energy Transfer Curves showing Trigger Paths Figure 13. Time Scale Showing Trigger Paths f x( ) ?e ?t? = P mett mett 0=( ) ?e ?t? Td t e ?t? = = p x( ) e fdt? fdt( ) x x! -------------------------= E X( ) xe fdW? fdW( ) x x! ----------------------------------- x 0= fdW== P mett 0=( ) fdW= P mett( ) P mett mett 0=( )P mett 0=( )= f= dWe ?t? Are Your PLDs Metastable? 6 Substituting for ? allows this variable to be expressed as a settling time constant of the flip-flop. Further, a synchroni- zation failure for a given clock cycle exists whenever a meta- stable event lasts a specified time (tr) or longer. Using these two substitutions, the probability that the flip-flop is metasta- ble in a given clock cycle is Eq. 9 Because the data transitions are independent, the number of failures in n clock cycles has a binomial distribution with an expected number of failures: Eq. 10 Assuming a sample clock frequency, fc, that represents the number of clock cycles, n, per unit time, the expected number of failures per unit time is Eq. 11 Assuming that all data transitions are independent and that the clock has a fixed period, the mean time between failures (MTBF) is Eq. 12 where MTBF is a measure of how often, on the average, a metastable event lasts a time tr or longer. Metastability Data The strong resemblance between Equation 12 and Equation 2 is based on the predictions of the first-order circuit analysis of an RS flip-flop. In fact, the metastability resolving time con- stant, tsw, is directly related to the variable t, which is based on the flip-flop's gain-bandwidth product. The device-dependent variable W depends mostly on the window of time within which the combination of the input and clock generate a metastable condition. This parameter also depends on process, temperature, and voltage levels. The MTBF equation is usually plotted with tr (the resolving time allowed for metastable events) on the X axis and the natural log of the MTBF plotted on the Y axis (see the appendix in this note). Because the metastability equation is plotted on a semi-log scale, the graph of tr vs ln(MTBF) is a line described by the equation Eq. 13 Graphically, the parameter tsw is 1/slope of the line on this graph. The equation for tsw from the graph is Eq. 14 To determine how often, on the average, a given synchronizer in a system will go metastable (MTBF), you must know the two device-specific parameters W and tsw, which should be available from the manufacturer. Table 1, discussed later in this note, lists these values for Cypress PLDs. Additional val- ues you need are the average frequency of both the system data and the synchronizer clock and the amount of time after the synchronizer's maximum clock-to-Q time that is allowed to resolve metastable events. For example, consider the method for determining the MTBF for a Cypress PALC22V10 registered PLD used as a synchro- nizer in a system with the following characteristics: In addition to these values, the PLD's maximum operating frequency, fmax, is taken directly from the data sheet. The frequency is specified as the internal feedback maximum op- erating frequency. It is calculated as where tcf is the clock-to-feedback time. If the data sheet does not specify tcf, you can use tco as tcf's upper bound. Using fmax, you calculate the amount of time that a metasta- ble event is allowed to resolve, tr, with Now you enter these values into the MTBF equation, making sure to keep all units in seconds: If the operating frequency of the system, fc, is simply changed to 33.3 MHz, 1 tsw ------- P fail1 clock( ) fdWe tr? tsw ------- = E failn cycles( ) nP fail1 cycle( )= E failunit time( ) fcfdWe tr? tsw ------- = MTBF 1 E failunit time( ) ------------------------------------- e tr tsw ------- fcfdW ---------------== MTBF( ) tr tsw ------- fcfdW( )ln?=ln tsw tr1 tr2? MTBF1( ) MTBF2( )ln?ln -------------------------------------------------------------------= W = 0.125 ps tsw = 190 ps fc = system clock frequency = 25 MHz fd = average asynchronous data frequency = 10 MHz fmax 1 tcf ts+ ---------------- 41.6MHz== tr 1 fc ---- 1 fmax -----------? 1 25MHz -------------------- 1 41.6MHz -------------------------? 16ns= = = MTBF e tr tsw ------- fcfdW --------------- e 16 10 9? s? 190 10 12? s? --------------------------------- 25 10 6 s 1? 20? 10 6 s 1? ? 0.125? 10 12? s?? ------------------------------------------------------------------------------------------------------------------ 59.7 10 33 s? 1.89 10 27 ? years Almost forever== = = = MTBF e 6 10 9? s? 190 10 12? s? --------------------------------- 33.3 10 6 s 1? 20? 10 6 s 1? ? 0.125? 10 12? s?? ----------------------------------------------------------------------------------------------------------------------- 623 10 27 ? s= = Are Your PLDs Metastable? 7 the system fails, on the average, about every 19,700 years--still beyond the system's normal lifetime. And if fc is changed to fmax (41.6 MHz), the system fails, on the average, every 9.62 ms. A 16-ns difference in resolve time, tr, results in almost 36 or- ders of magnitude difference in MTBF. Obviously, accurate data is needed to design a system with a high degree of reli- ability without being overly cautious. Characterization of Metastability Many authors (References 6, 8, 9, 10, 11, and 12) have per- formed numerous experiments on circuits to predict the like- lihood of device metastability. These researchers have used several testing theories and apparatus that can be classified into three basic types (Reference 14). Intermediate voltage sensors constitute the first type. Two voltage comparators determine whether the output voltage, Q, lies between two given voltages. The fixture produces an error output if Q has a level that is neither HIGH nor LOW, hence metastable. Figure 14 shows an intermediate voltage sensor. The second type of apparatus uses an output proximity sen- sor to determine if the Q and Q outputs have approximately the same voltages, which would indicate that the device is metastable. Figure 15 shows an output proximity sensor. The last type of apparatus uses a late-transition sensor to test for metastability. Note that if one or more gates separate the sensor from the metastable signal, the metastability might not be detected. The test circuitry must infer the occurrence of metastability by some other means. Figure 16 shows an ex- ample of a late-transition sensor. The sample input is detect- ed at time t1, then at a later time t2. If these two signals dis- agree, the device under test was metastable at t1. Information from Manufacturers Many semiconductor companies provide metastability data on their parts. However, most companies do not present the data in a format the engineer can use. They either present inconclusive and incomplete data or they assume the engi- neer can use the data without further explanation. Few com- panies compare their devices with similar devices. PLD manufacturers provide little data largely because of a fear that telling the design community that devices can fail in synchronizing applications will cause designers to use a com- petitor's parts. The truth is that no company can provide a device that is guaranteed never to become metastable when used as a synchronizer. At a given operating frequency, with a given asynchronous input, and given enough time, the de- vice becomes metastable. Cypress provides you with data you can use to build a system to any given level of reliability when using Cypress PLDs. Cypress has performed numerous tests and collected exten- sive data on Cypress PLDs, as well as PLDs from other com- panies. This data gives you a perspective of the parts that are best suited for a specific application. Specific data on the metastability characteristics of Cypress PLDs is found in this application note in the Test Results section. The Test Circuit Cypress uses a test that falls into the category of the late-tran- sition detection. Directly measuring the outputs of the flip-flop in a PLD are impossible due to the additional circuitry that lies between the flip-flop and the outside world. The metastability detection circuitry must, instead, infer the flip-flop's state. Figure 17 shows the metastability test circuit implemented in each test PLD. This circuit allows the PLD under test to effec- tively test itself. The device under test will both produce and record metastable conditions. Figure 18 is a state diagram showing the operation of the device. During normal operation, the two flip-flops' outputs (F1, F2) transition between states S1 and S2, depending on the synchronizer's state. During normal operation, the Exclu- sive-OR on these outputs produces a HIGH. This indicates either that metastability has not occurred within the device or that metastability that has occurred has resolved before the next clock cycle. If a metastable event cannot resolve before the next clock cycle, the state machine move to states S3 or S4. In this case, Figure 14. Intermediate Voltage Sensor Figure 15. Output Proximity MTBF e 0 10 9? s? 190 10 12? s? --------------------------------- 41.6 10 6 s 1? 20? 10 6 s 1? ? 0.125? 10 12? s?? -----------------------------------------------------------------------------------------------------------------------= Q HIGH THRESHOLD METASTAB LOW THRESHOLD Q VDD METASTAB Q Figure 16. Late-Transition Sensor METASTAB Q D Q D ASYNC INPUT CLOCK DELAY Are Your PLDs Metastable? 8 the state flip-flops have interpreted the signal from the syn- chronization register differently; exclusive-ORing this signal produces a LOW at the device's output, indicating that unre- solved metastability has occurred. This test circuit does not catch all metastable events. Specif- ically, it does not record metastable events that resolve before the next clock cycle. But metastability causes an error only when it has not resolved by the time the signal is needed. The Cypress tests thus reveal the information designers need to know: how often metastability creates an error in the system. The test circuit also includes the ability to check the maximum operating frequency of the device under test (Figure 19). At each clock edge, the first register's output toggles. When the device reaches its maximum operating frequency, the PLD array cannot resolve the changing signal fast enough to pro- duce a valid output. At this speed, one register might resolve the signal correctly and one might not, or both might produce invalid signal resolutions. In any case, when Exclusive-ORing the state T1/T2 of the two maximum-frequency testing regis- ters results in anything other than a HIGH, the part's maxi- mum operating frequency is exceeded. The Test Board A four-layer printed circuit board with two signal planes, a ground plane, and a power plane is used to perform the meta- stability measurements. Using this four-layer board gives a quiet testing environment with reliable, repeatable results. Figure 20 shows a block diagram of the test board, with the Figure 17. Metastability Test Circuit F1 Q D STATE REGISTERS Q D SYNCHRONIZER ASYNC CLOCK Q D Q D ERROR F2 Figure 18. Metastability Testing State Diagram SYNCH = 0, F1/F2 = 01 ERROR = 1 S1 SYNCH = 0, F1/F2 = 01 SYNCH = X, F1/F2 = 00 SYNCH = 0, F1/F2 = 01 SYNCH = X, F1/F2 = 11 S3 SYNCH = X, F1/F2 = 11 S4 ERROR = 0 SYNCH = X, F1/F2 = 00 ERROR = 0 SYNCH = 1, F1/F1 = 10 SYNCH = 1, F1/F1 = 10 SYNCH = X, F1/F2 = 00 ERROR = 1 S2 SYNCH = 1, F1/F1 = 10 SYNCH = X, F1/F2 = 11 Figure 19. Maximum Operating Frequency Test T1 Q DT CLK Q VCC CLOCK Q D T2 Q D FAIL Are Your PLDs Metastable? 9 complete schematic shown in Figure 21. The device under test (DUT) is decoupled with 0.01-mF and 100-pF capacitors. The test circuit is designed to fit all industry-standard and Cy- press-proprietary PLDs. The socket allows DUT pins 1, 2, and 4 to serve as clock pins. Pin 3 is the device's asynchronous input. The ERROR condition is located on pin 27 of a 28-pin device, and the FAIL condition is on pin 20. Two additional outputs, F1 and F2, monitor the state of the metastability test circuit flip-flops. All inputs and outputs connect with BNC connectors located around the board. The clock line, which is terminated with a 50 resistor to match the coax input impedance, is buffered with a 74AS04 and isolated from other signals by a ground trace. The input line is also terminated with a 50 resistor and buffered with a 74AS04. Four PLDs drive a four-digit LED display that counts metastability occurrences. Figure 20. Metastability Test Board Block Diagram METASTABILILITY EVENT DISPLAY EVENT COUNTINGRESET METASTABILITY ASYNC_IN CLOCK TESTING ERROR F1 F2 FAILMAXIMUM FREQUENCY TESTING Figure 21. Metastability Test Board Schematic CK I I I I I I I I VSS!OE O O O O O O O O VCC U3 PAL16R8 E 1 D 1 C 1 D P 1 E 2 D 2 G 2 C 2 D P 2 B 2 A 2 F 2 C C 2 C C 1 B 1 A 1 G 1 F 1 U6 LED7SEG CK I I I I I I I I VSS !OE O O O O O O O O VCC U2 PAL16R8 U1C 74AS04 ERROR FAIL BNC2 U1D 74AS04 C4 .01 ?F CK I I I I I I I I VSS!OE O O O O O O O O VCC U5 PAL16R8 C5 .01 ?F CK I I I I I I I I VSS !OE O O O O O O O O VCC U4 PAL16R8 DUT1 28PSKT R3 50 U1A 74AS04 CLOCK BNC BNC2 R4 50 U1B 74AS04 ASYNC_IN BNC E 1 D 1 C 1 D P 1 E 2 D 2 G 2 C 2 D P 2 B 2 A 2 F 2 C C 2 C C 1 B 1 A 1 G 1 F 1 U7 LED7SEG C7 .01 ?F RESET C6 .01 ?F C3 100 pF C2 .01 ?F U9 BANANA VCC U10 BANANA GROUND R7 10K U8A 74AS04 U8B 74AS04 C1 10 ?F SW1 PB SW U1E 74AS04 F1 BNC F2 BNC U1F 74AS04 Are Your PLDs Metastable? 10 After going LOW in response to a metastable event, the ER- ROR signal automatically transitions HIGH again at the next system clock. This LOW-to-HIGH pulse produces a clock to the input of the first PLD, which in turn increments the display of metastable events. When a digit reaches 9, the next occur- rence of metastability generates a cascade signal to the next higher digit. In this way, the test board can record a maximum of 9,999 metastable events. If a metastable event is received at 9,999, all LEDs switch to E, indicating that an overflow condition oc- curred. A reset button resets all counters and initializes the DUT. Test Set-Up Figure 22 shows a block diagram of the test set-up used for metastability testing. Two independent pulse generators (Hewlett-Packard 8082As) produce the CLOCK and the ASYNC_IN signal to the test board. A Tektronix DAS9200 logic analyzer records metastable events. A 2465 CTS digital oscilloscope with frequency counter accurately determines the DUT's maximum operating frequency and the ASYNC_IN and CLOCK frequencies. Test Procedure Cypress has tested all its 20-, 24-, and 28-pin PLDs. The fastest speed grades of each device type were tested be- cause these devices have the best metastable resolution time and thus make the best synchronizers. Several parts from each device type were tested to ensure an average metasta- bility characteristic for that product. Where possible, parts from different date codes were selected to eliminate varia- tions among different wafer lots. Testing for a specific device starts by creating the high-level description written in VHDL to be used with the Warp2 VHDL Compiler. Figure 23 lists the behavioral description used for generating a JEDEC file. All devices were programmed using JEDEC files generated by Warp2. Figure 22. Metastability Test Set-Up TIMER DAS9200 LOGIC ANALYZER HP 8082A PULSE GEN HP 8082A PULSE GEN TEK VOLTAGE SUPPLY ASYNC CLOCK VCC DEVICE UNDER TEST METASTABILITY EVENT DISPLAY TEST BOARDFAIL 2465 CTS OSCILL package test is component metastability port ( clock, async_in, reset : in bit; fail, perror, f1, f2 : out bit); end component; end test; entity metastability is port ( clock, async_in, reset : in bit; fail, perror, f1, f2 : out bit); end metastability; use work.bv_math.all architecture fsm of metastability is signal sync : bit; signal tsync : bit; signal t1,t2 : bit; signal f1_tmp, f2_tmp : bit; signal error_tmp : bit; signal fail_tmp : bit; begin proc1: process begin wait until clock = '1'; sync Are Your PLDs Metastable? 11 Each part is programmed, then tested for its maximum oper- ating frequency, fmax. By attaching the FAIL output to the os- cilloscope and observing the clock frequency at which the device started to malfunction (FAIL going LOW periodically), the maximum operating frequency for that part is determined. fmax indicates the maximum rate at which metastability mea- surements can be taken with accurate results. Above this fre- quency, metastable events are indistinguishable from errors caused by exceeding fmax. To determine each device's metastability characteristics, measurements are taken of the number of metastable events that occurred in a given time interval for several different clock and data frequencies. Equation 13 can be used to describe the graph of the meta- stability characteristics of the device: The slope of the line, tsw, can be determined only by forcing the Y intercept of the graph (ln(fcfdW)) to a constant value when using Equation 14: Note that tsw is a constant, device-specific parameter. proc2: process begin wait until clock = '1'; f1_tmp Are Your PLDs Metastable? 12 Because W is also a constant, device-specific parameter, it is only necessary to hold the product fcfd constant to make ln(fcfdW) constant. The independent variable tr is varied by changing fc to produce changes in the dependent variable ln(MTBF). Decreasing the frequency fc from its fmax value in- creases the metastable resolution time, tr, and decreases the probability that a metastable event will last longer than tr. As fc is decreased below a certain limit, the MTBF becomes too large to measure accurately. A metastable event occur- ring every minute is chosen as the upper limit for MTBF mea- surements. The range of clock rates for metastability testing is then between fmax and the metastable-event-per-minute clock rate. Between these two rates, a selected frequency constant (fcfd) ensures that no point in this range has a clock frequency less than twice the data frequency. This is because a data signal that transitions more than once per clock period cannot be effectively sampled. After determining this constant, data is taken from several test points within the test range by varying fc and fd. The data at each test point is averaged among all test devices, and the equation for the line through these points is determined using a linear regression analysis. The correlation between the line and the data points verifies that the metastability equation accurately describes the test data. From the calculated re- sults, the constants W and tsw are extracted. Test Results Table 1 and the Appendix list the results of the metastability analysis of Cypress PLDs. Table 1 also lists the maximum data book operating frequency, fmax; the metastability equa- tion constants, W and tsw; the metastability resolve time, tr, required for a 10-year MTBF; and the process for that part. You can use this data to determine the maximum metastabil- ity resolve time (tr) that you must use in a system to yield a given degree of reliability. The graphs and constants (W and tsw) can be used with any speed grade of the device, but it is suggested that the fastest speed grade of the specific PLD be used for optimum synchronizer performance. These graphs indicate the time (tr) and the device's minimum clock period that must be used to produce a desired degree of reliability. For example, to determine the operating parameters of the Cypress PALC22V10-20 from Table 1 when using the device as a synchronizer, determine the desired MTBF. With a 10-yr (315 ? 106 s) MTBF, for instance, a synchronization failure will occur once every 10 years on the average. The maximum operating frequency (fmax) from the PALC22V10's data sheet is 41.6 MHz. From this information, you can determine the minimum time (tr) beyond the device's minimum operating period that must be added for metastability resolution: This analysis assumes that the clock, fc, operates at fmax (41.6 MHz) and that the average asynchronous data frequen- cy is no more than half the clock frequency. The latter condi- tion ensures effective data sampling by the synchronizer. fd, as explained in the Statistical Analysis of Metastability section represents the rate at which the data changes state. fd is twice the average frequency of the asynchronous data input be- cause, during any given asynchronous data period, the asyn- chronous data changes state twice: once from LOW to HIGH and again from HIGH to LOW. Because either of these state changes can cause a metastable event, fd must be set to twice the average asynchronous data frequency when deter- mining the worst-case MTBF. Due to the real-world uncertainty in factors such as trace de- lays and the skew in clock generators, 5 ns is used instead of 4.73 ns for tr. The synchronizer's maximum operating fre- quency, fc, in this system is then The effective MTBF using these new values for tr and fc is MTBF e tr tsw ------- fcfdW ---------------= tr tsw MTBF( )ln fcfdW( )ln+( )= tr 0.190 10 9? s?( ) 315 10 6 s?( )ln 41.6 10 6 ? 41.6? 10 6 ? 0.125? 10 12? ?( )ln+ [ ] = 4.73 ns= fc 1 ts tcf tr+ + -------------------------- 1 10ns 12ns 5ns+ + -------------------------------------------------- 37.0MHz=== MTBF e 5 10 9? s? 0.190 10 9? s? ------------------------------------ 37.0 10 6 s 1? ? 37.0? 10 6 s 1? ? 0.125? 10 12? s? ---------------------------------------------------------------------------------------------------------------------------- 1.57 10 9 ? 49.7 years== = Table 1.Metastability Characteristics of Cypress PLDs. Device fmax (MHz) W (s) tsw (s) tr for 10-yr MTBF (ns) PALC16R8-25 28.5 9.503E?12 0.515E?9 14.68 PLDC20G10-20 41.6 3.730E?12 0.173E?9 4.91 PALC20RA10-15 33.3 2.860E?12 0.216E?9 5.87 PALCE22V10-7 100 32.35E?12 0.347E?9 10.56 PALC22V10B-15 50.0 55.76E?12 0.261E?9 8.19 PALC22V10-20 41.6 0.125E?12 0.190E?9 4.73 CY7C331-20 31.2 0.298E?9 0.184E?9 5.91 CY7C335-100 58.8 0.288E?12 0.189E?9 4.95 CY7C344-20 41.6 0.966E?9 0.223E?9 7.55 Are Your PLDs Metastable? 13 Another example focuses on the CY7C330-50 used as a syn- chronizer in a system whose output registers are clocked at an fc of 35.7 MHz, and the data has an average frequency of 10 MHz. The MTBF for this device used as a synchronizer is calculated by first determining the metastable resolution time, tr, allowed for synchronization. The maximum operating fre- quency of the part is specified in Cypress's Data Book as where tco in this case specifies the clock-to-feedback delay, and ts specifies the set-up time of the output registers. tr is calculated with the equation: With this result, the MTBF is This equation uses the same values for W and tsw with this 50-MHz device as with the 66-MHz device listed in Table 1. As stated previously, the constants listed inTable 1 are valid for all speed grades of a specific device. Also note that the 10-MHz average data frequency is doubled to produce the frequency of data transitions, fd. The last example illustrates how to use a Cypress PALC22V10C-10 as a synchronizer. For a 10-year MTBF, as- suming the maximum fc from Cypress's Data Book and fd, the required tr is Using this result, the synchronizer's maximum operating fre- quency is reduced from 90.9 MHz to Two-Stage Synchronization As explained earlier, you can use a second register in series to perform two-stage synchronization (Figure 4). This is ac- complished by feeding the output of the first synchronization register to the input of the second synchronization register. In PLDs, this method is common because the first synchroniza- tion stage can synchronize the asynchronous input signal, and the second synchronization stage can perform a Boolean function on a combination of the input and output signals. Boolean functions can be performed at either stage; the metastability characteristics listed in Table 1 apply to PLD registers' asynchronous inputs that are used directly as well as asynchronous inputs used as a Boolean combination of existing inputs and outputs. When implementing a two-stage synchronizer in a PLD, the probability that a synchronizer is metastable after the second stage of synchronization is the square of the probability that a synchronizer is metastable after the first stage of synchro- nization. The MTBF equation is From this result, the equation for tr becomes Using this result for a two-stage synchronizer in a Cypress PALC22V10C, the tr for a 10-year MTBF is reduced from 13.0 ns to The maximum fc increases from 41.6 MHz to This example shows that if the cycle of latency caused by the additional synchronization stage is acceptable, you can dra- matically increase the synchronizer's maximum operating fre- quency. fmax 1 tco tis+ -------------------= tr 1 fc ---- 1 fmax -----------? 1 35.7MHz ------------------------- 1 50.0MHz -------------------------? 8 ns= = = MTBF e 8 10 9? s? 0.290 10 9? s? ------------------------------------ 35.7 10 6 s 1? ? 20.0? 10 6 s 1? ? 1.02? 10 12? s? ------------------------------------------------------------------------------------------------------------------------ 1.31 10 9 ? 41.6 years== = tr 0.547 10 9? s?( ) 315 10 6 s?( ) 90.9 10 6 90.9 10 6 8.08? 10 15? ????( )ln+ ln[ ] 13.0 ns= = fc 1 1 fmax ----------- tr+ --------------------- 1 1 90.9MHz ------------------------- 13.0ns+ -------------------------------------------------- 41.6MHz= == MTBF e tr tsw ------- fcfdW --------------- 2 = tr tsw MTBF( ) 2 fcfdW( )ln?+ln( ) 2 ----------------------------------------------------------------------------------= tr 0.5( ) 0.547 10 9? s?( ) 315 10 6 s?( ) 90.9 10 6 90.9 10 6 8.08? 10 15? ????( )ln+ ln[ ] 7.65 ns= = fc 1 1 fmax ----------- tr+ --------------------- 1 1 90.9MHz ------------------------- 7.65ns+ -------------------------------------------------- 53.6MHz= = = Are Your PLDs Metastable? 14 References 1. Lubkin, S., (Electronic Computer Corp.), "Asynchronous Signals in Digital Computers," Mathematical Tables and Other Aids to Computation, Vol. 6, No. 40, October 1952, pp. 238-241. 2. Nootbaar, Keith, (Applied Microcircuits Corp.), "Design, Testing, and Application of a Metastable-Hardened Flip-Flop," WESCON 87 (San Francisco, CA, Nov. 17-19, 1987), Electronic Conventions Management, LosAngeles, CA 90045. 3. Stoll, Peter A., "How to Avoid Synchronization Problems," VLSI Design, November/December 1982, pp. 56-59. 4. Chapiro, Daniel M., Globally-Asynchronous Locally-Syn- chronous Systems, Stanford University, Department of Computer Science Report No. STAN-CS-84-1026, Octo- ber 1984. 5. Horstmann, Jens U., Eichel, Hans W., Coates, Robert L., "Metastability Behavior of CMOS ASCI Flip-Flops in The- ory and Test," IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February 1989, pp. 146-157. 6. Wormald, E.G., "A Note on Synchronizer or Interlock Ma- loperation," Professional Program Session Record 16, WESCON 87, November 17-19, 1987, Electronic Conven- tions Management, Los Angeles, CA 90045. 7. Pechouchek, Miroslav, "Anomalous Response Times of In- put Synchronizers," IEEE Trans. Computers, Vol. C-25, No. 2, February 1976, pp. 133-139. 8. Chaney, T. J., "Comments on `A Note on Synchronizer or Interlock Maloperation," IEEE Trans. Computing, Vol. C-28, No. 10, Oct. 1979, pp. 802-804. 9. Couranz, George R., Wann, Donald F., "Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region," IEEE Trans. Computers, Vol. C-24, No. 6, June 1975, pp. 604-616. 10.Veendrick, Harry J.M., "The Behavior of Flip-Flop Used as Synchronizers and Prediction of Their Failure Rate," IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 2., April 1980, pp. 169-176. 11.Kacprzak, Tomasz, Albicki, Alexander, "Analysis of Meta- stable Operation in RS CMOS Flip-Flops," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 1, February 1987, pp. 57-64. 12.Flannagan, Stephen T., "Synchronization Reliability in CMOS Technology," IEEE Journal of Solid-State Circuits, Vol. SC-20, No. 4, Aug 1985, pp. 880-882. 13.Wakerly, John F., A Designers Guide to Synchronizers and Metastability, Center for Reliable Computing Technical Re- port, CSL TN #88-341, February, 1988 Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA. 14.Freeman, Gregory G., Liu, Dick L., Wooley, Bruce, and McClusky, Edward J., Two CMOS Metastability Sensors, CSL TN# 86-293, June 1986, Computer Systems Labora- tory, Electrical Engineering and Computer Science Depart- ments, Stanford University, Stanford, CA. 15.Rubin, Kim, "Metastability Testing in PALs," WESCON 87 (San Francisco, CA, Nov. 17-19, 1987), Electronic Con- ventions Management, Los Angeles, CA 90045. Are Your PLDs Metastable? 15 Appendix A. Metastability Graphs of Cypress Devices 0 5 10 15 20 1.00E?05 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress PALC16R8-25 Tr (ns) 0 1 2 3 4 5 6 1.00E?04 1.00E?02 1.00E+00 1.00E+02 1.00E+04 1.00E+06 1.00E+08 1.00E+09 Cypress PLDC20G10-20 Tr (ns) Are Your PLDs Metastable? 16 Appendix A. Metastability Graphs of Cypress Devices (continued) 0 1 2 3 4 5 6 7 1.00E?05 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress PALC20RA10-15 Tr (ns) 0 1 2 3 4 5 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress PALC22V10-20 Tr (ns) Are Your PLDs Metastable? 17 Appendix A. Metastability Graphs of Cypress Devices (continued) 0 1 2 3 4 5 6 7 8 9 1.00E?07 1.00E?05 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress PALC22V10B-15 Tr (ns) 0 2 4 6 8 10 12 1.00E?05 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress PALC22V10D-7 Tr (ns) Are Your PLDs Metastable? 18 Appendix A. Metastability Graphs of Cypress Devices (continued) 0 1 2 3 4 5 6 7 1.00E?07 1.00E?05 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress CY7C331-20 Tr (ns) 0 1 2 3 4 5 6 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress CY7C335-100 Tr (ns) Are Your PLDs Metastable? ? Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Appendix A. Metastability Graphs of Cypress Devices (continued) 0 1 2 3 4 5 6 7 8 1.00E?07 1.00E?05 1.00E?03 1.00E?01 1.00E+01 1.00E+03 1.00E+05 1.00E+07 1.00E+09 Cypress CY7C344-20 Tr (ns)




Article Comments - Are your PLDs metastable?
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top