Using a personal computer to program the AT89C51/C52/LV51/LV52/C1051/C2051

5-3 Using a Personal Computer to Program the AT89C51/C52/LV51/LV52/C1051/C2051 Introduction This application note describes a per- sonal computer-based programmer for the AT89C51/C52/LV51/LV52/C1051/C2051 Flash-based Microcontrollers. The pro- grammer supports all flash memory microcontroller functions, including code read, code write, chip erase, signature read, and lock bit write. When used with the AT89C51/C52/ LV51/LV52, code write, chip erase, and lock bit write may be performed at either five or twelve volts, as required by the device. Devices sporting a "-5" suffix are intended for operation at five volts, while devices lacking the suffix operate at the standard twelve volts. The programmer connects to an IBM PC-compatible host computer through one of the host's parallel ports. Required operating voltages are produced by an integral power supply and external, wall- mounted transformer. Software Software for the programmer is available by downloading it from the Atmel BBS at 408-436-4309. The programmer is controlled by soft- ware running on the host. The AT89C51/C52 and C1051/C2051 have dedicated control programs, which were written in Microsoft C. Programs dedi- cated to the AT89LV51/LV52 do not exist; these devices are supported by the programs for the AT89C51/C52, respec- tively. In the text below, all references to the AT89C51/C52 may be assumed to apply to the AT89LV51/LV52 as well. All programmer control programs are invoked from the DOS command line by entering the program name followed by "LPT1" or "LPT2" to specify parallel port one or two, respectively. If the parallel port is not specified, the program will respond with an error message. The control programs are menu-driven, and provide the following functions: Chip Erase Clear code memory to all ones. The suc- cessful operation of this function is not automatically verified. Program from File Write the contents of the specified file into device memory. The user is prompted for the file name, which may require path and extension. The file is expected to contain binary data; hex files are not accepted. The first byte in the file is programmed into the first location in the device. Successive bytes are programmed into successive locations until the last location in the device has been programmed or until the data in the file has been exhausted. Programming occurs regardless of the existing contents of device memory; a blank check is not automatically per- formed. After programming, the contents of device memory are not automatically verified against the file data. Each programmed location in the device receives the maximum programming time specified in the data sheet. This is done because timing is enforced by soft- ware; the programming status informa- tion provided by DATA polling and RDY/BSY is not utilized. The control program provides no visual indication that programming is in progress. The main menu is redisplayed when programming is complete. 0285D-B?12/97 8-Bit Microcontroller with Flash Application Note Microcontroller5-4 Verify against File Compare the contents of code memory against the con- tents of the specified file. The user is prompted for the file name, which may require path and extension. The file is expected to contain binary data; hex files are not accepted. The first byte in the file is compared to the first location in the device. Successive bytes are compared to successive locations until the last location in the device has been compared or until the data in the file has been exhausted. Locations which fail to compare are displayed by address, with the expected and actual byte contents. If there are no compare failures, nothing is displayed. Save to File Copy the contents of device memory to the specified file. The user is prompted for the file name, which may require path and extension. The number of bytes in the resulting file is the same as the number of memory locations in the device. Blank Check Verify that the contents of device memory are all ones. Only pass or fail is reported; the addresses and contents of failing locations are not displayed. Read Signature Read and display the contents of the signature bytes. The number of signature bytes and their expected contents var- ies between devices. Refer to the device data sheet for additional information. Write Lock Bit 1 Write Lock Bit 2 Write Lock Bit 3 Set the indicated lock bit. Note that the AT89C1051/C2051 contain only two lock bits, while the AT89C51/LV51 and AT89C52/LV52 contain three lock bits. The state of the lock bits cannot be verified by direct observation. Exit Quit the programmer control program. System Dependency The control programs for the AT89C51 and AT89C52 come in two flavors: host system-dependent and host system- independent. System-dependency results from the use of software timing loops to enforce required delays, the dura- tion of which will vary between host systems running at dif- ferent speeds. The code provided was tested on an 80386- based system running at 33 MHz, and may require modifi- cation for use on other systems. This method was chosen for its simplicity. Host system-independence is achieved by using the Pro- grammable Interval Timer embedded in the system hard- ware to enforce time delays independent of system speed. The timer is reconfigured when the control program is invoked and restored to its original state before the pro- gram terminates. In order to guarantee that the program is not exited before the timer configuration is restored, the CTRL-C and CTRL-BREAK keys are disabled. This means that the program cannot be aborted except by specifying the exit option at the main menu or by rebooting the sys- tem. The timer control code is provided as an 8086 assembly language module, which is linked with the compiled control program. The granularity of the timer is 0.838 microsec- onds, but the minimum practical delay is system- and soft- ware-dependent. The timer code ensures that the delay produced will not be of shorter duration than requested. The control programs provided for the AT89C1051/C2051 are system independent. Programmer The programmer circuitry (see Figures 1 and 2) consists of the host interface and switchable power supplies. The sig- nal sequencing and timing required for programming is generated by the host under software control. A 40-pin ZIF socket is provided for programming the AT89C51/C52; the 20-pin ZIF socket accommodates the AT89C1051/C2051. Note that the power and ground connections and bypass capacitors required by the TTL devices are not shown on the schematic. Power for the programmer circuitry and the AT89C51/C52/ C1051/C2051 is provided by a fixed five volt supply. A sec- ond supply provides either five or twelve volts, selectable, for use during programming. The addition of a transistor to the output of the variable supply provides a third level, ground, for use when programming the AT89C1051/C2051. The resistor values utilized in the variable power supply cir- cuit were determined using the equations presented in the LM317 voltage regulator data sheet. Power supply ramp rates are accommodated by the host software. For 5 V- VPP programming, the devices must be ordered from the factory as an AT89CX-XX-5 (not available with the AT89C1051/2051). The programmer is connected to the host with a 25-con- ductor ribbon cable. To minimize the effect on signal integ- rity, the length of the cable should be as short as possible, preferably not exceeding three feet. Parallel Interface The original parallel interface provided by IBM was proba- bly not intended to support bidirectional data transfers. However, due to the way in which the interface was imple- mented, bidirectional transfers are possible. Over the years, many products have appeared which exploit this capability. Unfortunately, many system and interface card manufactur- ers have not faithfully cloned the IBM design, resulting in bus contention when the peripheral attempts to drive return Microcontroller 5-5 data into the interface. Usually the peripheral drivers can overpower the interface drivers and the peripheral works, though this is not considered a good design practice. Most parallel interfaces are now implemented in a single chip, such as the 82C411 or 16C452. These chips allow their output drivers to be disabled under software control, providing true bidirectional operation. The programmer software automatically enables bidirectional operation when used with parallel interfaces utilizing the 82C411, 16C452, or similar chips. Note that these chips also possess a mode control pin which must be at the correct level to enable the directional control feature. As a result, parallel interfaces utilizing these chips cannot be assumed to be bidirectional. If the programmer writes devices, but fails to verify, or the signal levels at the interface don't meet TTL specifications, the parallel interface may be incompatible with the pro- grammer. A design is provided (see Figure 4 and Figure 5) for a parallel interface which supports bidirectional opera- tion and is compatible with the programmer. This design is simple, requiring only six ICs. The interface can be strapped to appear as LPT1 (addresses 378-37F hex) or LPT2 (278-27F hex) and will be recognized by the POST when the host system is powered up. Due to its simplicity, the parallel interface CANNOT be used as a printer inter- face. Microcontroller5-6 Figure 1. AT89 Series Programmer Interface Note: 0.1 ?F bypass caps on all ICs Microcontroller 5-7 Figure 2. Power Supply for AT89 Series Programmer Microcontroller5-8 Figure 3. AT89 Series Programmer Socket Wiring Microcontroller 5-9 Figure 4. A Parallel Interface Supporting Bidirectional OperationA3 A4 A5 A6 A28 A27 A26 A25 1 2 3 4 U? A7A2434 U?B 74LS04 A8A235 U?C 74LS04 6 LPT2 LPT1 1 2 3 JP? HEADER3 A9 A22 AEN9 U?D 74LS04 8A11 5 6 11 12 74LS30 Y1 Y2 Y3 Y0 5 6 74LS139 A B G 42 7 DRD* 11 9 12 10Y1 Y2 Y3 Y0A B G DWR* CWR* 74LS139 A1 IORD* IOWR*B13 B14 A30 8 3 1 ISAbus connections 14 13 15 74LS04 10 12 U?E U?F 74LS04 11 13 U?B U?A Note:0.1-?FbypasscapsonallICs. Microcontroller5-10 Figure5. RSTDRV SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 D0 D7 D6 D5 D4 D3 D2 D1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 0C >CLK A9 A8 A7 A6 A5 A4 A3 A2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 A7 A6 A5 A4 A3 A2 A1 Y8 A8 G1 G2 D4 D3 D2 D1 CLR >CLK Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 ISA bus connections DRD* DWR* 4 5 12 13 9 1 CWR* 1 2 3 4 5 6 7 8 12 11 10 9 R?2 3 6 7 11 10 15 14 U? 13 12 11 10 15 25 24 23 22 2 3 4 13 14 15 16 STROBE* AUTOFD* INIT* SLCTIN* 1 14 16 17 5 18 6 19 7 20 8 21 9 P? DB25-S R? 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D0 D1 D2 D3 D4 D5 D6 D7 8 x 120 ohm 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 1 11 18 17 16 15 14 13 12 11 U? 9 2 3 4 5 6 7 8 1 19 74LS541 B2 U?A 21 74LS04 74LS175 8 x 120 OHM Note: 0.1-?F bypass caps on all ICs.