Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Amplifiers/Converters

Parallel 1-D FFT implementation with TMS320C4x DSPs

Posted: 26 Oct 1999 ?? ?Print Version ?Bookmark and Share

Keywords:digital signal processors? fast fourier transforms? partitioning? parallelization? id?

The purpose of this application note is to investigate efficient partitioning/parallelization schemes for one-dimensional (1D) FFTs on the TMS320C40 parallel processing DSP. This document focuses on complex FFTs; however, the concepts used can be easily applied to real FFTs. This paper covers both Decimation-in-Time (DIT) and Decimation-in-Frequency (DIF) methods of computation to give flexibility in programming and to demonstrate the results of parallelization on both methods.

View the PDF document for more information.

Article Comments - Parallel 1-D FFT implementation with...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top