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Taking new stabs at programmable analog

Posted: 01 Mar 2000 ?? ?Print Version ?Bookmark and Share

Keywords:pld? fpga? programmable logic? asic? lattice?

Stephan Ohr discusses two trends in programmable logic.

Programmable logic has some traditional advantages over ASIC design. The gate count of FPGAs approaches that of custom circuits. FPGAs can be programmed?and re-programmed?out in the field, enabling fast time to market. ASICs, in comparison, need careful attention to layout and fabrication technology. It can take anywhere from six weeks to two years (depending on the complexity of the circuit) to get an ASIC working properly.

But because of the means by which they are programmed (e.g., blown fuses) the configurations of programmable logic are not always as versatile as a full gate array or ASIC. And the cost?even in production volumes?seldom get down to the cost of a production ASIC.

Ongoing comparisons between ASICs and FPGAs have been the subject of many articles and conference papers. The subject will be addressed again at this year's International IC China Conference and Exhibition (IIC China 2000). For example, "Adapting ASIC Designs for use with FPGAs," will be the subject of a Xilinx presentation in Beijing on March 20-21, Shenzhen on March 23-24 and Shanghai on March 27-28 (

From my perspective, Asian engineers would be wise to pay attention to two trends in programmable logic. One is the trend toward putting DSP functions in programmable logic. This trend effectively hardwires DSP mathematical functions in FPGAs, and capitalizes on the fact that many operations will perform faster that way than when executed on a software-programmable DSP. The other trend, which seems to fail and re-surface again, is to use programmable logic (or EEPROMs) to execute analog functions.

The trend toward putting DSP functions in programmable logic is clearly a winner. Continued advances in DSP support entirely new applications in communications and entertainment. DSP makes possible advances in home theater such as DVD, HDTV, and digital audio surround sound. By compressing or expanding the sampled data stream according to mathematical formulas (polynomial functions), DSP paves the way for the transmission of video and high-resolution images over narrow bandwidth phone lines or cellular telephone systems. All of these applications stem from the DSP's ability to manipulate, filter and control digitized analog signals with fixed-point mathematical operations?most built on fast multiply-accumulates. In effect, the DSP contorts the phase, frequency and/or amplitude of an analog signal into a strange constellation, with each shift representing a specified set of data symbols.

As it turns out, the architecture of FPGAs and PLDs lends itself toward parallelizing many redundant DSP operations. Programmable logic manufacturers like Altera and Xilinx have repeatedly demonstrated in past IIC conferences that many DSP functions, hardwired into a PLD or FDGA, will often execute faster than on a general-purpose DSP. This is especially true for error correction and other expansion codes, in which check bits are added to a transmitted data stream according to a polynomial scheme (that is, according to a complex mathematical formula). In communications applications and data storage, for example, these codes ensure that correct data can be extracted through a noisy, error-prone transmission media.

Altera has marketed DSP functions?software algorithms?along with their chips for some time (in an effort, perhaps, to ensure their usability). The most popular MegaCores are Reed-Solomon and Viterbi decoders, says Craig Lytle, a frequent presenter at IIC conferences who now serves as Altera's director of IP business. Altera also has a "Megafunction Partners Program," a network of third-party providers who develop DSP algorithms that can be instantiated in programmable logic.

Other megacores offered by Altera include DES data encryption devices, FFT processors, and adaptive equalizers. By implementing these functions in programmable logic, it is possible to offload a general-purpose programmable DSP, if not displace it. "Many of the control and data movement functions would still be controlled by the DSP," says Lytle. "But the use of DSP functions in programmable logic would allow the designer to use a US$5 device instead of a US$60 part." Altera's presentation at IIC China 2000, by Paul Chan, Danny Mok and Martin Won, will discuss data switch design using programmable logic.

Programmable analog?

The convenience?the "hands on" friendliness of programmable logic?has tricked many engineers into thinking that analog design can be performed this way. Instead of making selections from a cluster of separate opamps, comparators and passive components; wiring prototypes with a clip block or soldering pencil; or farming a bulky PCB out to some design shop, is it possible to get all these things together on one chip, and then use (say) a Windows 98 programming tool to configure the device on a PC? Could you use PLD (or EEPROM) technology to configure and wire the analog components or cells? The answer is: Yes, it is possible. And there are certainly a number of EEPROM and PLD manufacturers willing to try it. The real question, is it a good idea? My analog experience suggests, maybe not.

PLD maker Lattice Semiconductor, for example, recently introduced a memory-programmable array for analog circuits. The company's "ispPAC" family is called the "PLD of Analog Chips," allowing designers to field-configure analog filters with an array of on-chip amplifiers and passive components. The Lattice ispPAC mimics past efforts by IMP Inc. and Motorola SPS (and less ambitious efforts by Xicor) to create a market for field-programmable analog arrays. Motorola called their chip an "FGPA for analog," while IMP's circuits were called "EPAC," for electronically programmable analog circuit.

These devices are certainly more efficient for prototyping than mixed-signal ASICs or linear arrays. These arrays, once marketed by companies like Micro Linear Corp., GEC Plessey, STMicroelectronics and AT&T Microelectronics (now Lucent Technologies) would include dozens of NPN and PNP transistors in various sizes, resistors and capacitors. The user could create a circuit by simply specifying the metallization pattern to connect the components.

The problem with linear arrays, however, was that they were expensive and difficult to use. Wiring them properly would require a considerable amount of analog expertise, not always available in the user community. Suppliers would complain that users would need a considerable amount of guidance and "hand-holding," and that the success rate on first silicon was only something like 65 or 70 percent. A bigger problem was the expense of these devices: Considerable if die utilization was only something like 50 percent and some big driver transistors were left unused.

Certainly, a field-programmable linear array would seem a more efficient method of prototyping analog circuits. The cost would be considerably less (less than US$20 a chip), the programming tools could include some built-in analog expertise, and the time to market would be fairly rapid. But none of these field-programmable analog arrays seemed to attract a large market following. Nobody really wants these devices, at least not in enough volumes to support an entire product line. My opinion is that they work against the economics of analog design.

Lattice's "PLD for analog," for example, can be programmed to function as an analog filter with various poles and rolloff characteristics. Ease of use?a key concern for beginners to analog design?is promoted by a Windows 98-based program, which allows engineers select filter components and parameters, simulate their the effects on filter performance, and then program the PLD to perform the chosen function.

It seems to me, there's two ways to build a filter front end. Either you use some discrete op amps and R-Cs (in multiple stages, if you like) to design an analog filter, or you go completely digital, with a general-purpose DSP. The DSP will be extraordinarily precise, even adaptive, but it will take some programming effort and?along with the ADCs and DACs required?will cost you about US$30. The analog filter will be much sloppier in comparison, but "good enough" for a lot of high-volume applications. It will cost you about US$1.58.

It is between these extremes?both in precision and price?that the programmable analog devices have tried to fit. The Motorola part was about US$20; the IMP EPAC was about US$9. Lattice prices theirs around US$7 in volume. But will this be enough to move the market? Easy-to-use filter design software, similarly, is readily available for other applications besides programmable analog. National Semiconductor and Texas Instruments, for example, give out simple Spice programs to aid in opamp selection for that US$1.58-filter. These days, you can go to a website to use a filter design tool online?at National's site, for example.

The PLDs and FPGAs may have an advantage over separate components in "space constrained" applications, but considering that analog components like op amps come in SOT23 and chip scale packages, it's hard to imagine an analog PLD having any advantage in portable design. Certainly, programmable analog will have an advantage in rapid prototyping. It will offer advantages over a solder pencil or clip block for trying out amplifier circuits with leaded components.

I can only repeat Lattice's conjecture here and wish them well: "The world thought we were crazy when we introduced a US$35-PAL to replace US$4-worth of SSI and MSI. Now programmable logic is a US$2.3-billion industry."

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