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Timing-Driven Flow (TDF) SLI ASIC design flow with commercial EDA tools

Posted: 11 Feb 2000 ?? ?Print Version ?Bookmark and Share

Keywords:toshiba? taec? tdf? eda? asic?

The Timing-Driven Flow (TDF) is the first state-of-the-art design methodology based on open EDA tools and standards to successfully address the challenge of deep sub-micron timing convergence. Without TDF it is not uncommon for a high-gate-count, high-complexity design with tight timing specifications to go through 10-20 iterations between synthesis and layout and still fail to meet timing. This application note describes the function of the TDF in an ASIC application.

View the PDF document for more information.



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