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Controlled impedance design and test

Posted: 31 Mar 2000 ?? ?Print Version ?Bookmark and Share

Keywords:intel? oem? pcb? motherboard? tester?


? Intel's Labs Controlled Impedance Design and Test Intel Corporation ? Intel's Labs Agenda zStatement of Objective zBackground zAC Timing and Signal Quality zImpedance Fundamentals zDesign Guidelines zTesting Board Impedance (TDR) zSummary and Conclusions ? Intel's Labs Objective The objective of this presentation is to provide information to assist OEMs and PCB vendors to design and test motherboards which will meet a 28 (+/- 10%) impedance specification ? Intel's Labs Background z Existing motherboards are designed around 65 +/-15% z The new 28 +/-10% specification is required by the memory channel z Exceeding the specification results in additional channel timing error and reduced signal margin z Both effects may cause failures on the memory channel ? Intel's Labs Signal Quality and Timing z RDRAM Channel is designed for 28 z Impedance mismatch causes signal reflections z Reflections reduce voltage and timing margins z AC Timings are tight! 2X clock @ 400MHz Operation = 1.25ns window Only 100 - 150 ps allowed for total channel timing error PCB impedance is only one factor z PCB process variation -> Z0 variation -> Channel error THIS IS WHY HITTING 28 IS CRITICAL ? Intel's Labs RDRAM Signal Routing Chipset Data /Control Path Chipset Differential Clock Pair CK133 DRCG Clock Path CTM CFM ? Intel's Labs z Data is sampled on both edges of the clock 625ps data window z 0.8V low signal swing between logic 0 and 1, signal swing reference at 1.4V Data Signal and Sampling Differential clock 18 bit data Vterm = 1.8V Vref = 1.4V Vol = 1.0V Valid Data Sampling Window 625ps Valid Data Differential clock ? Intel's Labs Impedance Fundamentals z Microstrip vs Stripline z PCB Parameters and Relationship to Impedance z Simulation Tools (Field Solvers) and Impedance Calculators z PCB Materials z Chipset Example ? Intel's Labs 0LFURVWULS;6HFWLRQ H W S T Z0 = F(W,H,T,) EQUATIONS FOR Z0 USED IN ZCAL PROGRAM ? Intel's Labs 6WULSOLQH;6HFWLRQ H2 T W S H1 B Z0 = F(W,H1,H2,T,) EQUATIONS FOR Z0 USED IN ZCAL PROGRAM ? Intel's Labs PCB Parameters z H tolerance is hardest to control z W & T has less impact due to wider trace z Z0 can be calculated from geometries Equations (like zcalc) are approximate 3D Field Solvers also used to calculate impedance z Plot of Z0 variation with various parameters (W, H, r, T) shows impact Also show what tolerances we need to hit for the various geometries ? Intel's Labs Z0 vs H (W=18mils, T=1.4mils, r=4.5) 4 4.2 4.4 4.6 4.8 5 26 26.5 27 27.5 28 28.5 29 29.5 30 30.5 H (mils) Z(Ohms) Z0 vs H ? Intel's Labs Z0 vs W (H=4.5mils, T=1.4mils, r=4.5) 16 17 18 19 20 26.5 27 27.5 28 28.5 29 29.5 30 30.5 31 W (mils) Z(Ohms) Z0 vs W ? Intel's Labs Z0 vs r (H=4.5mils, W=18mils, T=1.4mils) 4.2 4.4 4.6 4.8 5 5.2 27 27.5 28 28.5 29 29.5 30 er Z(Ohms) Z0 vs er ? Intel's Labs Z0 vs (H=4.5mils, W=18mils, r=4.5) 1 1.5 2 2.5 3 28.15 28.2 28.25 28.3 28.35 28.4 28.45 28.5 28.55 T (mils) Z(Ohms) Z0 vs T ? Intel's Labs Impedance Calculation z 3D Field Solvers are most accurate HP, Ansoft, Sonnet, Polar etc z Z calculators based on equations are also pretty accurate 3D Field Solver vs ZCALC#1 #2 #3 #4 #5 #6 H 4.5 4.5 4.2 4.8 4.5 4.5 W 18 18 18 18 17 19 W1 18.1 18.1 18.1 18.1 17.1 19.1 T 1.4 2.8 1.4 1.4 1.4 1.4 r 4.5 4.5 4.5 4.5 4.5 4.5 Z0 (3D) 29.0 28.4 27.6 30.4 30.2 27.9 Z0 (zcalc) 29.1 28.7 27.7 30.4 3.02 28.0 ? Intel's Labs PCB Materials z PCB tolerances determine Z0 variation Dielectric thickness, trace width, plating thickness, dielectric constant and solder mask thickness z Pre-preg style type and characteristics determine H variation single ply vs. 2-ply resin content and tolerance flow tolerance z Recommended material tolerances: Dielectric height tolerance +/- 10% (~ 0.4mil) Trace width tolerance +/- 3% (~ 0.5mil) Pre-preg resin content tolerance +/- 3% Pre-preg resin flow tolerance +/- 3% er tolerance +/- 5% (~0.2) @ 1GHz H W S T ? Intel's Labs Design Process z Specify material to be used z Calculate board geometries for desired impedance - or use example stackup z Build test boards and coupons z Measure board impedance using TDR Need accurate data - follow TDR methodology z Measure geometries with x-section z Adjust design parameters and/or material as required z Build new board and re-measure May require one or two iterations ? Intel's Labs Design Guidelines z Several reference stackups provided z Test coupon should be included on panel If possible, integrate test coupon pattern into board Makes lot sampling easier, more accurate Test coupon probe pattern ? Must match probe type Gerber file is available z Don't forget about other traces on PCB! Need to adjust other trace widths to meet impedance requirements for different busses ? Intel's Labs Recommended Stackup z Numerous variations are possible z We used the following as a starting point: W=18mil, H=4.5mil, T=2.0, 1 ply 2116 pre- preg G G 4.5 mils 2.1 mils 6 mils 18 mils10 mils S Don't forget ground floods and stitching ? Intel's Labs Inner Layer Routing z Also numerous possible stackups z We used the following as a starting point: W=13.5mil, H1=7mil, H2=5, T=1.2 G G 5 mils RIMM 28(UNLOADED): 1.2 mils 5 mils 13.5 mils6 mils S 7 mils 1.2 mils 1.2 mils ? Intel's Labs Testing Board Impedance z TDR Basics z Test Equipment z Test Coupon z Test Procedure z HVM Testing z Reference Collateral ? Intel's Labs TDR Basics z High-edge rate pulse transmitted to DUT z DUT reflects wave z Reflected wave measured by scope z Impedance of DUT determines reflected voltage amplitude z Scope and/or software calculates impedance based on reflected wave amplitude PLOT OF TDR OF SHORT/OPEN/50 OHM z Propagation delay can also be measured ? Intel's Labs TDR of 50 Ohm Load ? Intel's Labs TDR of Open ? Intel's Labs TDR Test Equipment z Tektronix 11801C using SD24 TDR test head z HP54750A HP54753A Single Ended TDR HP54754A Differential TDR z Polar CITS500S ? Intel's Labs Test Coupon z Use test coupon for ease of testing Gerbers for an example coupon are available z Test coupon placement Coupon can be designed as part of motherboard Ideally located in memory section of board Or have separate coupon somewhere on panel z Test coupon probe pattern Pattern depends on test equipment and probes Land pattern must match test probe used GND ? Intel's Labs Test Coupon GND TDRManualProbeType X-Section 3"&6" G G 4.5 mils 2.1mils 6mils 18mils10mils S ? Intel's Labs Test Coupon Design z Test coupon routing should match routing guidelines for RDRAM bus Follow trace to trace spacing rules Ground shields required to control etch and reduce coupling Ground traces will affect trace impedance, so they must be included in test coupon z Signal trace routing Route straight (no bends) for best results End of trace should be open - no pad or via z Ground pads required for probing Microstip - Signal and ground pad Stripline - Signal and pad for each reference plane ? Intel's Labs Test Procedure z Equipment calibration is critical Careful calibration is required for accurate results Procedure is defined in TDR Methodology Doc 28 Ohm standard should be used to verify test setup z Probing techniques Standard high-frequency probes are acceptable Discontinuity at probe tip must be minimized ? Minimize ground lead length ? Probe ground pad should be near signal pad z Reading the data Impedance will vary along transmission line Ringing will also affect measurement ? (Beginning (near probe) of line will have more error ? Intel's Labs TDR Measurement z Display Adjustment: Line launch pt on first column. Reflection on last column Utilize vertical scaling to maximize screen Maximize the display Proper display adjustment is important Launch Region Reflection Region Launch Edge Reflected Edge ? Intel's Labs TDR Measurement z Measure the response correctly: Region should be after midpoint slightly before reflection region Take average impedance of the mean region Measure the average mean Measure the right region and take average Left Limit (50%) Right Limit (70%) Mean Region Launch Reflection ? Intel's Labs 28 Ohm TDR Plot ? Intel's Labs Rambus 28 Measurement z Determine equivalent error at probe tip Calibrate against a standard Standard can determine error Standard Instrument + Cable + Probe = Total Error Standard ? Intel's Labs Rambus 28 Measurement z Compare standard value against measured value Measure standard with cable connected z Use difference between measured and actual z Shift spec window by that amount z Example: Calibrated value = 25 Ohms Measured value = 27 Ohms Difference = + 2 Ohms Use error as an offset Shift measurement window by error value ? Intel's Labs Standards z Option 1)*preferred ? 28 ohm airline ? 15 cm min length z Option 2) ? Two 50 ohm airlines connected in parallel (25 Ohms) ? 15 cm min length Standard value must be close to spec Airline standards provide best accuracy ? Intel's Labs HVM Testing z Test at 100% for early production Avoid excursions on first production units Use recommended TDR test probes z Lot to Lot checks (sample) Once stability of materials & process have been established z Frequent calibration recommended Use 28 Ohm calibration standard Use Intel recommended calibration method for offset calculation z Place coupon in middle of panel to minimize error Or a minimum of 0.8" from edge of panel z X-section data to check for process variations ? Intel's Labs Reference Collateral Collateral By Available PCB Test Methodology Doc Intel WWW TDR Theory (AN 1304-2) HP WWW URLs: Company URL Intel Corporation Hewlett-Packard Tektronix Polar ? Intel's Labs Summary and Conclusion z Meeting 28 +/-10% requirement is critical for a solid motherboard design z Board and trace geometries can be calculated, or use reference design z Material tolerances need to be analyzed using x-section measurements z Test builds will be required to dial in process z Accurate impedance measurements are required to verify design

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