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Long road ahead for analog synthesis

Posted: 01 May 2000 ?? ?Print Version ?Bookmark and Share

Keywords:mixed signal? analog synthesis? ohr? hdl? gds?

Stephan Ohr examines the problems and advances in analog synthesis.

It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital.

Designers of analog and mixed-signal ICs, especially if they've come from the digital design world, want to input a hardware description language (HDL) file, push a button, and automatically output a GDS-II file. They will then want to hand that file to a silicon foundry (like UMC, TSMC or Chartered Semiconductor), and say, "Here, build this for me." In truth, this is not quite so simple even for digital circuits, but the situation gets much worse in analog since there is no such thing as "analog push-button design."

Unlike digital circuits, whose manipulation of ones-and-zeros can be described on a relatively high level of abstraction, analog (mixed analog-digital) circuits manipulate physical entities?voltages and currents in the time domain?and are typically dependent on the behavior of physical structures. Thus, every part of the analog design?from simply describing the circuit, to simulating its performance, to physically laying it out?will seem much more complicated and time-consuming than digital designs. Time-to-market pressures on designers of consumer and communications ICs (which incorporate lots of analog and mixed-signal technology, such as amplifiers and line drivers) will make analog design feel like torture.

The problem has to do with how digital circuit behavior is represented. Digital circuits effectively manipulate ones and zeros, and these can be represented by flashing lights, by CMOS transistor switches, or (in the case of IBM's early computers) by clicking relays whose coils are driven by vacuum tubes. This separation of logical circuit behavior from any kind of physical implementation allows for relatively effective digital circuit synthesis to proceed in two stages. In the first stage, a synthesis engine will examine the high-level language statements (in Verilog, VHDL, or C/C++), and find the gate-level circuitry (the NAND, NOR, OR gates or multiplexers) that will generate the patterns of ones and zeros demanded by the register-transfer level (RTL) statements. The logic circuits (like NAND or NOR gates) describe a particular combinatorial function (like two data zeros at the input will generate a data one at the output) independently of the physical circuit implementation.

In the next stage, the synthesis tool matches the logic circuit to the capabilities of a particular ASIC fabrication process (like 0.25?m or 0.18?m CMOS) or a particular programmable logic architecture (such as from Altera or Xilinx). The second stage is usually trickier than the first, since the drive capability and clocking requirements (along with layout variables and interconnect parasitics) can produce timing anomalies among parts of the circuit that are supposed to trigger concurrently. But these anomalies can be discovered and optimized with the static timing and critical path analyzers widely available from tool vendors like Cadence, Mentor Graphics, Avant!, Synopsys and Monterey Design Systems.

The behavior of analog circuits, in contrast, is described by voltages and currents, and these are tied to load conditions (resistive, capacitive and inductive) as are fabrication processes. Analog transfer functions (the rise and fall of voltages and currents over time) might be represented by analog extensions to Verilog, VHDL and even C, but linking these "automatically" to specific circuits and fabrication processes is extremely unreliable. It assumes certain intelligence or reasoning ability that these tools do not have yet.

Apart from university researchers, two companies are conducting the most interesting development work in analog synthesis. These are Antrim Design Systems and Barcelona Design. Antrim's approach, which borrows heavily from university research, is decidedly "Top Down." It seeks to integrate design flows for analog cells and components in the same design flows as digital. Barcelona's approach (one that analog designers instinctively gravitate toward) is decidedly "Bottom Up."

The better approach?

Antrim's approach to synthesis is similar to what early EDA proponents called "silicon compilation." Like digital synthesizers, the Antrim synthesis engine will extract a circuit topology, i.e., high-level language statements comprising Verilog and its analog extensions (Verilog-AMS). But instead of formulating a logic or amplifier circuit with low-level granularity, the synthesis engine will search through a library of pre-characterized cells that may be useful in the implementation of the topology. Such an approach requires a fairly large library of analog circuit functions and cells. It also mandates a good method of finding these library components.

Much of this work builds, in fact, on analog synthesis techniques developed by professors Rob Rutenbar and Richard Carley at Carnegie Mellon University (CMU), Ranga Vemuri and his students at the University of Cincinnati, and Georges Gielen at the Catholic University of Leuvin, Belgium. The original ASTRX/OBLX synthesis tools developed at CMU, for example, would search bipolar cell libraries for parts that would match the requirements of a high-level specification. Development work at the University of Cincinnati, using VHDL as the high-level specification language, effectively raises the level of abstraction for ASTRX and OBLX tools, but a successful design effort still depends on a large cell library (and the ability to locate those cells quickly).

Rutenbar's efforts at CMU have concentrated on harnessing multiple computers (networked Sun workstations, for example) to the search for relevant analog circuits. CMU has managed to operate as many as 24 workstations in parallel. Analog synthesis utilizes a numerical optimization engine that evaluates alternative designs, and picks the best one, Rutenbar explained. But this has an extraordinary cost in terms of computer run time.

"To be really effective, the synthesis engine must visit a large number of designs?100,000 or more," Rutenbar said. "That's about 5 or 6 Spice runs for each circuit visited, equivalent to over 500,000 Spice runs." This will take days or weeks if one computer has to perform every one of the simulations one-after-another. That gets 'expensive' if you have to simulate each one of them. Typically, you're looking for short cuts." Parallelizing the evaluation mechanism will invariably cut runtime. A power amplifier circuit, for example, with 100,000 alternatives came up with the best topology with 10 CPU hours on a network with 20 Sun UltraSparc workstations."

Vermuri's students at Cincinnati have similarly developed a "Branch and Bound" algorithm that automates an exhaustive search for alternative circuit topologies to synthesize. Designs are entered in VASE (a VHDL-AMS Synthesis Environment) and the synthesis process produces a netlist of sized components that optimizes circuit area and performance variables. Spice models embedded in the synthesis system are used to evaluate architectures and components suggested by the search mechanisms.

Critics of this "search-all/use-some" approach, like Dataquest analyst Gary Smith, claim that "it doesn't work." More charitable observers concede that, if it works, the process takes too long. More than a day of computer runtime to design an otherwise simple opamp can feel excessive (especially where computer time-share users are charged US$0.50 for each CPU second!). While Antrim Design's tools build on much the same compilation model, they too seek to streamline the search process. Antrim's engineering and management staff includes veterans of HSpice pioneer Meta-Software, and PSpice developer Microsim. The company's Antrim-MSS tool uses "a guided search," according to vice president of marketing, Leslie Spruiell.

The Antrim synthesis tool uses optimized models to drive the compiler, and the compiler depends on a library of working circuits. Though they are represented as behavioral models (to run fast on the search-and-evaluate engine), the circuits are based on characterization data drawn from actual silicon. In effect, Antrim's synthesizer uses behavioral models (drawn from actual characterized cells) to synthesize (that is, compile) new SoC circuits.

When operating the Antrim synthesizer tool, the user develops a "synthesis plan" (a top-level view of the circuit), and sets performance expectations. The synthesis plan represents a programmed series of steps for circuit partitioning, model selection, sizing and optimization. Its design parameters are specifications that serve as optimization variables. The plan will also include steps for process retargeting. Because it depends on the personal input of experts, synthesis is far from a "push-button" operation. But where working models can be culled from an existing library, a lot of manual labor in the creation of new analog intellectual property (IP) can be eliminated.

The synthesis tool devised by Barcelona departs from the search tree algorithms developed at CMU and more recently tweaked by Antrim. Barcelona's approach actually begins with a model of specific functions in specific processes. The models are process specific, and are provided by the foundry vendors who will most probably fabricate the completed parts. TSMC, for example, maintains an extensive library of analog functions. The library is not highly touted or promoted, since TSMC (in its charter as a foundry) cannot do anything that may be construed as competition for its customers. Nonetheless, it maintains a rather sophisticated library of analog functions. A forms-based tool?accessible only online at Barcelona's website?encourages engineers to modify the parameters of the analog function, to perform a simulation on Barcelona's server, and to explore whether the device can meet all the input specifications while still being manufacturable.

Barcelona's design system is currently available for op amps, though switched capacitor filters and data converter functions will be available at some future date. Because it starts with an existing circuit, this method of perfecting analog ICs is closer to "optimization" than "synthesis." It will, nonetheless, save a week or two for an experienced analog engineer, which may be several months of learning time for engineers with no analog experience.

The Barcelona tool so impressed veteran analog designer Bob Dobkin (founder of Linear Technology Corp.), that he made a personal investment in the company and took a seat on its board of directors. Joe Costello, former president of Cadence Design Systems, found this company compelling enough to end his voluntary retirement from EDA and serve on the board too! We're sure to see more activity in the analog design automation arena in the near future.





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