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FPGAs/PLDs??

170MHz FIFOs Using the Virtex Block SelectRAM+

Posted: 26 Jun 2000 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? fifo? first in first out? memory? virtex?

This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 512-by-8 FIFO, with the depth and width being adjustable within the Verilog code.

View the PDF document for more information.



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