Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

24-bit magnitude comparator with 50ns response

Posted: 01 Sep 2000 ?? ?Print Version ?Bookmark and Share

Keywords:atmel? fpga? pga? gate array? programmable logic?

This application note demonstrates how to implement the AT6000 Series FPGA as a magnitude comparator that can compare two 24-bit binary integers in 50ns.

View the PDF document for more information.

Article Comments - 24-bit magnitude comparator with 50n...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top