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FPGAs/PLDs??

16-bit four-to-one multiplexer with 15ns delay

Posted: 01 Sep 2000 ?? ?Print Version ?Bookmark and Share

Keywords:atmel? fpga? pga? gate array? programmable logic?

This application note demonstrates how to implement the AT6000 Series FPGA as a 16-bit four-to-one multiplexer with a 15ns delay from the select control to the most significant output bit.

View the PDF document for more information.



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