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Integrated approach for emerging tech designs

Posted: 01 Dec 2000 ?? ?Print Version ?Bookmark and Share

Keywords:dsm? synthesis? place and route? drc? rule checker?

Tools that integrate clock tree synthesis with logic synthesis, placement, route and interconnect extraction will have the power to maximize the potential of new process technologies in cell-based flows.

In the increasingly complex world of deep-submicron (DSM) process technologies, millions of objects are at the designer's disposal in a single design. In 0.25?m-process technologies, only large design teams using semi-custom and custom tools attempted these designs. Today, these large designs are implemented in design flows with standard cell synthesis and automatic place-and-route tools.

ASIC design teams would like to take advantage of the latest process technologies to implement very large designs with significantly smaller design teams. Leading-edge designs need the performance gains of new technology, and also need to get to the market quickly. New design automation tools are changing the DSM design landscape by enabling designs to meet their market window expectations. These emerging tools are opening doors to new horizons by merging logical and physical design processes into a single tool, creating the possibility of new design paradigms. One of the most significant ramifications of this merger can be found in the implementation of clock trees.

The clock specification for a DSM-class design has become more complex, due to DSM effects. A simple synchronous design with a single clock would need a clock specification that goes far beyond timing.

Current chip design flows consist of standalone point tools: synthesis, place and route, clock tree generators, extractors, delay calculators, static timing and signal integrity analyzers. With current approaches, it can be difficult to fully appreciate the subtle interconnect effects that occur at process technologies of 0.18?m and below. These interconnect effects modify all of the clock constraints and are becoming more than just commonplace?they are becoming critical.

Emerging EDA approaches directly address DSM effects during clock tree implementation by integrating all of the design functions of synthesis, place and route, timing and signal integrity into a single tool using a single, unified data model. This unified system enables a clock methodology of incremental refinement, which is the correct-by-construction approach. Starting with front-end constraints such as timing or skew, a clock tree can be constructed using collaboration between the design functions.

The final solution is achieved by gradually reducing delay uncertainty until the constraints are met while maintaining electrical and physical rules from the foundry (design rule checks, or DRCs).

? Mike Newman

Technical Marketing Manager

Magma Design Automation Inc.





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