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Timing margin analysis for clock buffers in high-speed synchronous networking systems

Posted: 27 Nov 2000 ?? ?Print Version ?Bookmark and Share

Keywords:pericom? clock output skew? clock skew? clock distribution? buffer ic?

This application note describes how skew has become a major constraint that forms the upper boundary for a system clock's frequency, and shows how to calculate timing margin and the minimum clock output skew.

View the PDF document for more information.



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