Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > T&M
?
?
T&M??

Testing dimensional limits of high I/O flip-chip design

Posted: 01 Feb 2001 ?? ?Print Version ?Bookmark and Share

Keywords:flip-chip? fea? cte? microintegration? solder bridge?

The study characterizes underfill materials, examining some large package geometries and design manufacturing processes to avoid defects for I/O counts.

View the PDF document for more information.



Article Comments - Testing dimensional limits of high I...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top