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Library generators employ optical correction at cell level

Posted: 01 Mar 2001 ?? ?Print Version ?Bookmark and Share

Keywords:ret? psm? moore's law? opc? cell-based asic?

The strong phase-shifting mask (PSM) technique is being touted by a few voices as the only possible savior of Moore's Law. These observers predict impending doom: "Evil subwavelength design geometries are coming!" But from out of the crisis, a new "non-EDA" EDA market was to be born, and cell-based design was to change in radical ways.

The challenge to Moore's Law starts with the lithography equipment in the silicon fab that prints IC design patterns on silicon wafers. Current equipment operates at the 248nm light wavelength, or 0.25?m. Subwavelength silicon, at 0.18?m and below, is distorted because the design features are smaller than the wavelength of light used to "paint" them. The most advanced, and extremely scarce, equipment is at 0.193?m wavelength; 0.157?m equipment is years away. Non-optical next-generation lithography equipment may be a decade away.

Consequently, resolution enhancement techniques (RETs) must modify design layouts to correct for subwavelength distortions. These corrections are offered by EDA vendors and rendered on masks by mask shops. Seeing a way to bridge the gap between IC design and manufacturing, EDA companies offered new RET software tools. For most ICs, at least down to 0.13?m, RET includes optical and process correction (OPC), scattering bars, attenuated/half-tone PSM and support for off-axis illumination. More expensive and complex "strong PSM" is reserved for high-volume, high-speed CPUs and RAMs, and for 0.1?m and 0.07?m research. At what point in the IC flow should this RET technology be applied? Let us consider how IC products are created.

Design flow

The typical IC design flow includes logic design, synthesis, place and route, and verification. The output is the final, verified version of the physical layout, or tapeout. Design data is then sent to be translated to proprietary mask-writing and inspection equipment formats.

The most common point of insertion for RETs, especially for advanced RET, is at tapeout-verification. In some cases of simple rule-based OPC, insertion occurs instead at the mask-writer format translation step. Unfortunately, mask shops have limited knowledge of the design and no way to verify the massive RET changes to layouts. As a result, advanced RET insertion during the mask-format translation stage is difficult to optimize, and risky.

The most logical point of RET insertion is squarely in the verifiable design flow. At this stage, designers control trade-offs, but retain flexibility in targeting a particular fab process. EDA companies have already integrated full-chip RET into the design-verification stage, where standard-cell placements are finalized?enabling distortions caused by full-chip cell interactions to be accurately corrected. Pre-correcting cells before placement in a full-chip context, as some propose, is a fundamentally flawed idea. So what is the implication for the cell-creation flow in the subwavelength era?

An exciting development in EDA is practical tools for automated generation of standard-cell libraries. Standard cells?IC building blocks?routinely determine design goals of performance, power, area and yield. A next step for these library-automation tools is to generate cells that are not only, for example, area-optimized, but also RET-compliant. RET compliance is enforced by special rules for the library generators. Thus, the cell library generator tool set presents an opportunity for enhancing yield, by enabling greater freedom for the full-chip RET tools set, within the context of crucial IC design goals.

New rules for RET compliance provide an excellent next step for the subwavelength IC flow. Strong PSM has a role, but it has been overstated. With RET-compliant cells, IC designers can make trade-offs during design without committing to RET application too early.

? Dan Nenni

Vice President of Marketing

Prolific Inc.





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