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Process design kits take aim at custom ICs

Posted: 15 Apr 2001 ?? ?Print Version ?Bookmark and Share

Keywords:pdk? asic? simulation tool?

Claiming to accelerate time-to-market for custom IC designers, Cadence Design Systems has announced the availability of Process Design Kits (PDKs) for 0.25?m and 0.18?m Taiwan Semiconductor Manufacturing Corp. (TSMC) processes. The PDKs contain process-specific information used with Cadence schematic, simulation and layout tools.

Cadence had developed PDKs on a custom basis during the past several years, but this announcement marks the first standardized offering, said Ed Lechner, group director of custom IC solutions marketing at Cadence. "There have been some shifts in the market such that we think it makes sense to do this in a manner more accessible to customers," he said.

ASIC flow

The PDKs are currently targeted toward full-custom design but could be used in an ASIC design flow to develop standard cells, Lechner said.

The TSMC PDKs support current versions of the Cadence Composer schematic environment, Spectre analog simulation tool, Virtuoso placement and routing system, and Assura and Diva verification suites. The PDKs provide process-specific information that's needed to make those tools work together smoothly in a full-custom flow.

For example, PDKs provide process-specific schematic symbols, along with software that ties the symbols to layout. PDKs offer parameterized cells, specific to the targeted process. The kits also include verification rules, layer maps and properties, connectivity information, and Virtuoso router setup data.

The TSMC 0.25?m and 0.18?m PDKs are available from TSMC's website, A 0.13?m PDK will follow later in the year. Kits are free to qualified TSMC customers.

? Richard Goering

CMP Media

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