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Optimizing DSPs for wireless world

Posted: 15 Apr 2001 ?? ?Print Version ?Bookmark and Share

Keywords:voip? dsp?

Development of 3G wireless communication applications has energized an industry that was already moving at a rapid pace. The complexity of next-generation requirements is taxing the capabilities of traditional DSP technology and design methodologies, and is causing industry business models to be redefined. In response, next-generation DSP design programs have expanded from a focus on increased performance, lower power and manufacturing-process enhancements to scalable, programmable and configurable DSP cores.

The market demand for DSP-based products is increasing. According to Forward Concepts, global DSP chip shipments are expected to experience a CAGR of 34.4 percent across 1999 to 2003, with chip shipments in 2001, for instance, expected to reach $8 billion. The majority of that growth can be attributed to the digital wireless market, but there is also great long-term potential growth for the Internet telephony market, including voice-over-Internet Protocol (IP), voice-over-asynchronous transfer mode, voice-over-frame relay, fax-over-IP and voice-over-digital subscriber lines.

DSPs that power those expanding and emerging applications are typically evaluated based on performance, cost (code size) and power consumption. More recently, those processors are also being judged based on the efficiency of their compilability, where fewer clock cycles consumed can translate directly into easier implementation, lower costs and faster time-to-market.

Process improvements

Demand for higher DSP performance, measured in millions of instructions per second (Mips), is growing exponentially. By comparison, 2G voice systems require only about 100Mips. The cost of the final system design is directly affected by how much off-chip memory the DSP core requires, which is determined mostly by code size.

A feature-rich 3G application, for example, is expected to require 10 times the amount of code that 2G designs need. Therefore, a viable 3G design can be achieved only by means of efficient coding.

A shift has already begun in order to meet the high-performance demands of complex next-generation voice and data applications. Manufacturers are exploiting new materials and processes as well as looking for new design methodologies and tools to develop next-generation processors.

Some recent semiconductor technology developments include copper interconnects, silicon-on-insulator and low-k dielectrics. Those new materials and processes also require the advent of sub-0.1?m lithography techniques in order to make small gate enhancements. As a result, the processors and platforms that power the next-generation of communication systems can take advantage of new high-performance, optimized architectures, such as parallel designs where multiple functions are carried out simultaneously.

DSPs and microprocessors are benefiting from those high-performance architectures. The newest cores that power such processors are being designed with optimized code size, clock cycles and power consumption. Optimizing the core or processor in those three dimensions makes the devices able to handle the high-performance demand of the latest applications. Those three optimization dimensions are also proving vital for delivering increased performance at low cost.

Another important parameter of the systems is the memory architecture. An efficient memory design enables reduced chip size and lowers cost. The memory hierarchy should exploit the available memory on the chip, both on level one and level two, as well as external to the chip. A good architecture will use memory efficiently, minimize the use of on- and off-chip memory and perhaps take advantage of a unified memory. The latest architectures should also be suited for multiple processes, making them scalable across different applications and platforms.

Future design architecture

To achieve optimal performance, future architectures also need to avoid high-speed data bottlenecks between cores, peripherals and memory. Whereas traditional systems were connected via bridges and a PCI backplane, future systems can benefit from connections via RapidI/O switches, which allow increased performance and eliminate bottlenecks due to simultaneous switching. Use of that technique will also drive the development of co-design and co-simulation tools.

While the features of 3G are driving the need for new processes, materials and architectural design concepts, they in turn are driving the need for improved electronic-design tools and methodologies. In contrast to traditional application-specific integrated circuit design, next-generation high-speed devices and embedded solutions require designers to take a system-level approach, which demands the use of EDA tools that offer a top-down view of an entire system.

With high-speed devices and embedded solutions, designers must consider the entire system as they architect a design. EDA tools need to offer co-simulation, where software execution and debugging, along with hardware evaluation, can occur simultaneously?even before hardware prototypes are available.

Since the need for co-simulation will only increase in the future, the industry must continue to enhance development tools to support the increased complexity of communication designs. As the tools that enable co-simulation continue to improve over the next few years, cores can be reused in other technology modes by extracting synthesizable models from the transistor-level intellectual property.

? Paul Marino

Vice President, DSP Core Technology

Motorola Inc.





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