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Multichip DRAMs serve graphics apps

Posted: 15 Apr 2001 ?? ?Print Version ?Bookmark and Share

Keywords:mcp? multichip package? graphics? 3d? sdram?

No technology can last forever. There will always be breakthroughs in the best and the latest technology as well as new challenges to it. So the question arises: how long can multichip package (MCP) solutions last in the diverse and rapidly changing graphics market?

To make a reasonable prediction, the background of MCP technology must be explored in detail, along with the competing option of embedding memory on graphics chips. In 1998 and the first half of 1999, graphics chip vendor NeoMagic claimed more than 50 percent of the worldwide market in portable graphics chip sets. Its success was due, in part, to use of embedded memory technology. In late 1998, MCP technology began spreading widely in the mobile graphics industry because of a decline in SDRAM prices and demands of a larger memory buffer size in portable PC graphics applications, especially in 3D imaging.

The theme behind this new trend is simply boosting laptops' graphics performance with more and faster memory at a more competitive price. Today, major graphics suppliers such as ATI, S3 and Silicon Motion have all started shipping their new-generation graphics controllers, which use MCP technology, to various laptop OEMs addressing different notebook market segments.

An MCP is the combined integration of separate controller ASIC die and memory die (or dice) into a single package. In most designs, these dice are connected using a common substrate, a special signal-routing technique and advanced wire-bonding technology. The final packaged device looks the same as any other standard controller package. It works exactly the same way as a controller that has an integrated or so-called embedded memory?and in some cases even better.

To determine the potential longevity and success of a new technology, you need to study its advantages and disadvantages. The MCP's advantages include such factors as cost efficiency, size, space and performance gain.

One of the key advantages of the MCP is cost efficiency. The cost of discrete memory is relatively low compared to embedded (customized) memory since discrete memory is a commodity product utilizing high-volume cost efficiencies of the same products sold in packaged form. Typically, multiple suppliers produce these discrete memories. This means that portable graphics chip set design houses and their procurement personnel have no sole-source concerns.

Flexibility is inherent

Such a business model also helps drive competitive memory pricing. Every time there is a memory die shrink or a density increase, the required new substrate of the MCP package can easily be implemented to accommodate new memory pad locations. Contrast this with embedded memory, where the entire ASIC must be redesigned to take advantage of more advanced fabrication processes.

In the chip industry, size is another important factor in the potential success of a product. The MCP uses its integration to its advantage in this area. To date, the largest embedded memory buffer size built into a mobile graphics controller (and perhaps in any other application) is a 6MB buffer. The complexity of the embedded design and the process differences between ASIC and memory are the major obstacles in increasing buffer size in embedded design. In general, ASIC fabrication uses a 5M1P (five-layer metal, one-layer polysilicon) or a 5M2P process and memory uses just the opposite: a 2M5P process. The design house has to match these two by converting cell libraries in order to put them in a single design. This increases the overhead in design resources and cost and may also result in an inefficient layout and larger die size for the embedded memory device.

Compact solution

Space is another key factor where the MCP comes out ahead. There is almost no space left to solder down graphics memory on motherboards, particularly in portable PCs. Thus, graphics controller designers seek creative ideas or technology breakthroughs to keep up with the demands of applications and try to make ASIC designs smaller and compact to save board space. This contributes directly to cost savings. For example, the slim type of notebook model includes features from the entire desktop PC, including a powerful CPU, system memory, video, audio and communication interfaces?all on one tiny motherboard.

Performance gain is a fourth area where MCP has an advantage. A point-to-point connection, between the ASIC and memory dice, in a mobile MCP graphics controller gives the controller's performance a big advantage. Such a connection greatly reduces the traditional heavy system loading that often generates noise, which limits overall performance. In addition, the trace length optimization on the MCP's substrate further reduces the skews and jitters from signals. A gain in video graphics performance of up to 10 percent has been observed in benchmarking tests because of such a unique configuration.

But every technology has disadvantages, and the MCP is no exception. Strong concerns are yield, power consumption, wafer testing and test implementation. Buyers and suppliers in the semiconductor business are naturally concerned with yield results: The better the package yield, the easier it is to make a profit. The average selling price of a mobile graphics controller in last year's third quarter was $22.30, according to Mercury Research. An MCP production line can easily run thousands or millions of units per month. If the package percentage yield drops by even a single digit, it would be easy for the loss to increase rapidly.

There is no way to recover either memory or ASIC once they have been wire-bonded and packaged. The buyer has to throw away the whole MCP, even if only a single bit of discrepancy is found on the display screen. Even though a memory manufacturer can provide wafer-level burn-in (for an added premium) to weed out marginal memory devices, such stress tests cannot guarantee 100 percent yield.

Power consumption is another concern for MCP suppliers and users. Long battery life is one of the most important features of a notebook PC. The typical power consumption of a 3D mobile graphics controller is about 2W to 3W. The internal memory contributes roughly 25 percent to 35 percent of the total graphics controller's power dissipation. These values were calculated with an engine-memory speed of 100/100MHz.

Nevertheless, according to the controller designers the engine speed will most likely be doubled in 2001 and so will the memory operating frequency. If this happens, the controller's power consumption could be drastically increased. Therefore, designers are driving the memory industry to adopt a lower supply voltage. They want 2.5V and perhaps further down to 1.8V, when memory operation is over 500Mbps/pin, in order to save power. A lower power supply also helps to reduce the heat generated from high-speed operation.

MCP wafer-level testing is a third concern. Memory suppliers may use a process flow that is slightly different from the packaged part when offering wafers to MCP customers. Wafer burn-in provides a series of stress tests to the memory device and aims to weed out most of the marginal parts on the wafer. In the EDS-II stage, wafer burn-in checks the operating and self-refresh current in addition to the standby and leakage current examined in the EDS-I flow. Memory vendors use this process to perform functionality tests and further screen out dynamic refresh failures after burn-in. Wafers are ready from this point to be shipped out for assembly.

The test program implementation is another important consideration. At present, test programs for the MCP are limited. That means that an isolated MCP customer developing new test programs for screening out the potentially failed or marginal parts could be in for a very tough job. Most controller customers own a tester or testers dedicated to ASICs. Since controller designers are familiar with the ASIC test environment, but not necessarily with memory tests, they are faced with another hurdle: developing a high-quality memory test program to perform effective MCP package sorting before shipment. However, major memory suppliers like Samsung have already implemented strategic services for their MCP customers.

Figure 3: Wafer burn-in (WBI) provides a series of stress tests to the memory device and aims to weed out most of the marginal parts on the wafer.

? Michael Chao

Manager, Graphics Technical Marketing

Samsung Semiconductor Inc.





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