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DRAM flavors shift for post-PC future

Posted: 15 Apr 2001 ?? ?Print Version ?Bookmark and Share

Keywords:fast-page-mode? dram? sdr? ddr? rdram?

As recently as 1994, the DRAM industry offered only the fast-page-mode (FPM) architecture. Now the industry manufactures not only fast-page-mode DRAM, but also a whole alphabet's worth of designs. There are extended-data-out (EDO) DRAM, SDR synchronous DRAM, DDR synchronous DRAM and niche DRAM architectures such as RDRAM. This mixture of architectures and varied densities, bus widths and package styles all contribute to today's extreme complexity of manufacturing and managing resources in a successful DRAM company.

Historically, the personal computer industry competed to build faster, smaller, less expensive white boxes. This constant momentum forced the DRAM community to accommodate many architectural changes. Consequently, all memory users, even those in non-PC applications, were forced to either redesign current working product to utilize the new commodity memory, or pay a higher price for a low-volume, low-bit-per-wafer, legacy memory.

For example, when the PC market required a memory solution that had higher density, was faster and consumed low voltage, the DRAM industry responded by developing the SDR SDRAM. The PC world rapidly transferred from established FPM-EDO DRAM architectures to the new SDR memory, but these changes were not backward compatible with the older technology. The new SDR memory required a lower supply voltage (3.3V), a faster clock (66MHz at the time), different package options and different interface timing.

Legacy costs

Because of the volume shift to the new SDR memory, legacy memory became much costlier to manufacture. This required the FPM-EDO memory user to pay higher prices for the legacy memory or implement costly product design changes in order to use it.

But times are changing. The DRAM industry is focusing on providing innovative, high-volume memory solutions to increasingly segmented markets. In fact, Micron Technology is devoting more of its resources to developing products supporting networking and communications. Most non-PC applications have longer development times than a typical PC design, although non-PC end products have a longer, more stable life?but the cost to make design changes can be high. As one response to the needs of the non-PC market, Micron continues to support 16Mb and 64Mb EDO DRAM. It is recommended that any new designs use one of the newer DRAM architectures.

As market segments proliferate, DRAM requirements become more fragmented. This causes a less-sustainable volume and inhibits the migration to one core memory architecture. Fortunately, the DRAM industry is working with the IEEE's Jedec to develop new standards promoting a managed-memory environment and a clear path for future memory expansion. This standardization allows a designer to use the most cost-efficient memory solution today and prepare for the natural migration of tomorrow's solution, all without worrying about DRAM obsolescence problems. This holds true for all standard memory technologies.

Pinout, packaging intact

The new Jedec standards define the same packaging and pinout for 64Mb through 512Mb DDR SDRAM devices, regardless of manufacturer. Thus a designer may develop a product line using a 200MHz, 4Mb x 16 DDR SDRAM today, when it is a low-cost commodity device, and migrate without design changes to the enhanced 266MHz, 32Mb x16 DDR SDRAM. The pinouts and standard packages for the x4, x8, x16 and x32 organizations, of both SDR and DDR parts, follow this same philosophy.

DDR SDRAM is currently being shipped with a transfer rate of 2.1GBps. Micron 2Mb x 32 DDR devices provide a data rate up to 400MHz, equating to a transfer rate of 3.2GBps.

The DDR SDRAM is a natural migration from the proven SDR SDRAM technology; the SDR and DDR cores are essentially the same. The designer can optimize designs on the fast DDR technology with very few enhancements from standard SDR memory. The key upgrades include a bidirectional data strobe (DQS) signal to capture data in a source-synchronous domain, a fast 2n-prefetch architecture that moves data on each clock edge, a standard SSTL_2 (2.5V) interface with differential inputs for all I/O, including the clock.

Lower-power DDR

Another benefit to incorporating DDR memory into a design is the lower power consumption. DDR memory operates at a 2.5V level, yet it provides data at twice the rate of SDR memory. With the industry-adopted Jedec standard data-sheet device, compatibility among all manufacturers is assured. DDR also promotes quick time-to-market solutions by using simple design and routing rules already available for the existing SDR technology.

If the high-speed DDR memory turns out not to be a requirement, the industry is committed to supporting current SDR memory through at least the 512Mb densities. There are many inherent benefits to these two architectures that may not be evident in the data sheets. For instance, most vendors have already developed wafers supporting both SDR and DDR on the same die.

Examinations of the 32Mb x 4 SDR and DDR functional block diagrams reveal the memory core is essentially the same. The fundamental differences are found in the data interface.

The SDR memory data interface is a fully synchronous design where the data captured is only on the leading clock edge. The DDR memory data is a true source-synchronous design, where the data is captured twice per clock cycle, with a bidirectional data strobe. This architecture employs a 2n-prefetch format where the internal data bus is twice the width of the external bus.

? Jeff Mailloux

Marketing Director

Computing and Consumer Group, Micron Technology Inc.





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