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Optimizing ASIC design flow for SoPCs

Posted: 01 May 2001 ?? ?Print Version ?Bookmark and Share

Keywords:asic? sopc? asic? hdl?

System-on-programmable-chip (SoPC) technology has characteristics of both board-based design and ASIC-based system-on-a-chip ASIC design. The immediate attraction of SoPC is that, like a breadboard, the design can be up and running very quickly.

However, many attributes of the ASIC design process remain, so it is worthwhile looking at design techniques and tools relevant for SoPC use. Can the fast prototyping it offers replace existing SoC ASIC design flows, or are they complementary technologies that combine to offer the greatest value to the designer?

The new generations of programmable logic devices bring them to the levels of complexity previously encountered in SoC ASIC design. The introduction of processor cores into the SoPC also introduces the need to consider software and hardware design and the software/hardware interface as integral parts of the design process adding further complexity to the design process.

SoC board designs

SoC design can, in broad terms, be described as a process of successive refinement. SoC designs start life as a collection of behavioral HDL or C models describing the functionality of the system. At this level, designers investigate the characteristics of the design?with abstract high-performance simulation models prior to committing to a full RTL description.

For complex designs such as those targeted for SoPC-class programmable logic, reaching 100 percent RTL can be a lengthy process, potentially taking as long as several months. In embedded systems, code development and debug is as much as 75 percent to 80 percent of the total design activity.

Using HDL simulators and hardware/software co-verification tools allows code to be executed, debugged and checked for correct interaction with the hardware while the detailed design is still under development. SoC designers who use co-verification have repeatedly reported savings in design schedules on the order of months through handling software and hardware development in parallel, reducing integration times after prototypes are available and eliminating the risk of finding errors after fabrication.

Software and hardware teams work together during development, using a single reference model of the design. The verification tools uncover problems in the design. These could be actual bugs or interface problems, but often they are inefficiencies in the design. Being able to refine both hardware and software leads to higher-quality designs.

One restraint on SoPC fast prototyping is the ability to build the prototype quickly. If the complete design can be fitted into a single device, this may be a very feasible approach. However, many designs may require additional support circuitry (often analog/RF) to complete the design functionality and allow appropriate connections to be made to facilitate testing of the device.

The usefulness of fast prototyping in these cases depends upon such factors as the time taken to fabricate the rest of the design?as opposed to the SoPC itself?and the ease with which suitable test patterns can be applied to the design.

Co-verification steps

How can you visualize both the hardware and software operation in a single flexible environment that allows fine grain control on the operation and complete debug facilities? One answer is co-verification, and this blurs the boundary at which "verification" ends and "design" starts.

For example, Mentor Graphics recently encountered a case where a software exception handler was being entered more than once for each exception. Tested stand-alone, both the hardware and software were functional?the exception handler correctly completed and returned. In the test cases applied, the hardware was functional. However, the multiple entry?and execution?meant that more cycles were consumed than required and could have led to problems if multiple exceptions occurred. We were able to track down and rectify the cause of this glitch by having visibility in both hardware (through the logic simulator) and software (in the debugger).

Co-verification tools offer significant advantages in the verification and analysis of hardware and software interactions over both standalone simulation techniques and running code on the physical system. The value of those techniques is greatest on the low-level code where the interactions are most complex. The value statement of co-verification tools has primarily been focused on verification of the hardware/software interface prior to fabrication.

With the ability to match the lab design stimulus and follow the code execution in the hardware/software co-verification tool, the designer can reproduce the problem and easily trace the cause of the observed behavior in a way that is just not possible on the prototype. Additionally, the designer can extract prototype waveform traces from the prototype design with a logic analyzer, which allows the traces to be manipulated into a format suitable for the HDL simulator connected to the hardware/software co-verification tools.

In an overview, hardware/software co-verification and other ASIC verification techniques will be essential weapons in the armory of designers and will enable full realization of the benefits of SoPC.

? Robert Kaye and John Wilson

Mentor Graphics

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