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Programmable system chips move forward

Posted: 01 May 2001 ?? ?Print Version ?Bookmark and Share

Keywords:psc? rtl? verilog? hdl? vhdl?

Using dedicated hardware to boost real-time performance of embedded systems is a common practice and with the introduction of PSCs (programmable system chips), we will see more widespread adoption. In the new era, many software engineers will learn how to use the inherent parallelism of hardware to boost performance of timing-critical software functions.

Development obstacles

The basic problem for developers of embedded software is designing software that will run fast enough in a real-time environment. Developers must have at least some knowledge of hardware design in order to use a PSC. The key to this knowledge is understanding that they are shifting design bottlenecks from serial software operations to parallel hardware functions.

After identifying the software bottlenecks that are candidates for hardware implementation, the system designer must determine the feasibility of a hardware implementation. The sense of what is feasible to implement in hardware is one of the first stumbling blocks to overcome for those not familiar with hardware design.

Beyond the algorithm implementations, the interface requirements must also be designed. When evaluating which PSC to use, make sure that the software-hardware interface meets the needs of your design.

After arriving at a basic hardware design, the software designer must then describe the hardware implementation for the logic synthesis tool that will feed the device vendor's programming software. The most popular logic synthesis tools start with a description at the RTL abstraction, which means that every operation has explicit hardware timing. The standard design language is an HDL, either VHDL or Verilog.

One industry trend that will make it easier for software developers to design hardware is the nascent support for the well-established software design languages (C, C++ and Java) for hardware design. Once support for these languages is viable, software engineers will not have to learn a new language.

Tools are available for using software languages for hardware design, but the paradigm for using these tools continues to evolve, and neither a standard coding style nor a standard design abstraction exists. At least four paradigms are in use in commercial or proprietary tools:

Paradigm 1?This uses a restricted subset of RTL for single-clock designs with the restriction that all hierarchical modules have registered outputs. This paradigm has the advantage of being able to yield very high-performance simulation of the design.

Paradigm 2?Called the RTL paradigm, this uses a Verilog-like overlay (in the form of a C++ class library) to implement RTL designs using C++. This paradigm mimics the common usage of the standard HDLs, but with a more familiar syntax.

Paradigm 3?This is known as the architecture level, where the storage requirements of the algorithm are "inferred" from the context. This provides an abstraction slightly above RTL.

Paradigm 4?This is the behavioral level. It attempts to automate the scheduling of parallel operations to remove the burden of identifying explicit storage elements from the software engineer.

Over the next two or three years, software language support for hardware design will evolve and the design community will probably settle on one or two of the four paradigms.

Paradigm shift

Perhaps the greatest advantage of adopting a programming language design paradigm rather than an HDL paradigm comes from the relative ease of interfacing the software to the hardware simulation.

The software developer can use the hardware simulation capabilities inherent in the chosen paradigm and can use familiar C/C++ debuggers to diagnose problems. After simulation, the developer has a language description of the design that simulates correctly. Now the developer must get from the language description to the programming files for the PSC.

In the standard programmable-logic hardware design flow, a synthesis tool, such as the Synplify Pro software, compiles an HDL description of the design into a netlist that specifies the interconnections among the programmable elements of the device. The netlist then feeds into the programmable logic vendor tools that map the circuit elements to specific circuit locations within the device and interconnect the elements as specified by the netlist and other designer controls.

If the PSC developer chooses one of the C/C++ paradigms, a good synthesis tool and the programmable logic vendor tools are still needed. For software developers who are unfamiliar with designing hardware, ease of learning and ease of use are the most important considerations for choosing a synthesis tool. The Synplify Pro software was designed to have a short learning curve, but also to have the power to produce excellent results quickly, especially for complex designs.

Over the next few years, the PSC design methodology will mature to the point that they will be widely used for system design. The problems surrounding design language paradigms will converge to a solution that inherently supports verification of mixed software/hardware systems and the debug support for hardware-accelerated software algorithms will support source-level, in-system debugging of hardware.

? Bob Erickson

Vice President of Engineering

Synplicity Inc.





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