Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Vendors should count silicon, not tapeout wins

Posted: 01 May 2001 ?? ?Print Version ?Bookmark and Share

Keywords:tapeout? eda software tools? chip design team? gdsii? working silicon?

Achieving tapeout is good, but boasting about the quantity of tapeouts puts emphasis on the wrong thing, says Robert P. Smith.

Robert P. Smith is vice president of marketing and business development for Magma Design Automation.

A curious phenomenon is gripping the electronic design automation industry and it is contagious. Several EDA software vendors have boasted recently about the number of tapeouts design teams have achieved while using their software tools. Tapeouts are certainly important, but I am concerned!as we all should be!about the amount of attention paid to tapeouts, when working silicon is what matters. Tapeouts are not an end unto themselves, but, rather a milestone on the way to the goal of working silicon.

I find the boasting about tapeouts to be particularly remarkable, given that some EDA vendors' software tools are far removed from the actual GDSII that links the design process with manufacturing. They can claim design wins through partial placement!they typically do not handle detailed routing or other necessary elements such as clock or power. By themselves, their tools cannot get a design to GDSII, the last handoff point before mask and manufacturing. Instead, they must rely on established physical design systems to do the "heavy lifting" needed to generate the clean, verified GDSII that signifies a successful tapeout.

To be fair, tapeout appears to mean different things to different people. A recent column in this publication quoted three people, each with a slightly different definition of tapeout. My definition of tapeout is when the database (typically GDSII) that contains the design information meets all of the complex process-specific design rules, has been fully verified and is ready to be used to generate masks.

Designers invest many thousands!maybe even millions!of dollars and much time to get working silicon that meets their performance objectives. Complex chips go through a long and rigorous design cycle. Tapeout is one of many important steps along the way, but so is mask set generation. How often do we hear people boast about that?

I believe the endless talk about tapeouts is misleading. Believing that the number of tapeouts is proof of the superiority of a new EDA tool is ludicrous. Chip-design teams are measured on their ability to deliver working silicon on schedule. Whether a particular EDA tool has taped out two designs or 20 is irrelevant!it is the ability of the tool to enable the team to meet their goal that counts.

A chip-design tool's strength is in its ability to generate high-quality designs that will give the best-performing, highest-quality silicon-based end product. To deliver that, the tool must address detailed technology and process rules and special considerations such as clock tree synthesis, power routing, signal integrity, electrical integrity and the like.

Achieving tapeout is good, but boasting about the quantity of tapeouts puts emphasis on the wrong thing. All in all, the issue today should be the ability to take a design from start to finish!to silicon!on time, on spec and within budget.

In the end, it is silicon that drives our industry, and it is silicon that is the ultimate goal of a design project.

Article Comments - Vendors should count silicon, not ta...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top