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Cadence's 'all-in-one' tool gets skeptic reviews

Posted: 01 May 2001 ?? ?Print Version ?Bookmark and Share

Keywords:rtl? integration ensemble? ie? primetime? superchip?

Cadence Design Systems Inc. presented only one user of its ballyhooed Integration Ensemble tool last February and competitors are already expressing considerable skepticism about the all-in-one tool.

Cadence calls Integration Ensemble (IE) the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file. The single-database tool is part of Cadence's SuperChip initiative, which will add analog design capabilities to IE's primarily digital focus.

"We think we are up to something big here today," said Ray Bingham, Cadence's president and CEO at the IE press conference. "These initiatives represent revolutionary technologies that would enable customers to design better, faster and more complex chips in less time."

At a follow-on user panel during the conference, it became clear that chip designers still need third-party point tools, even with IE. Of the five users on the Cadence panel, only one, Claude Frank, program director at STMicroelectronics, used the IE tool to complete his design. The rest used versions of PKS, Cadence's synthesis product, which is embedded within IE.

Frank said his group was happy with IE's results, which he said helped ST design the CB75 chip, which has 5 million transistors and was processed in 0.12?m, six-layer copper technology. But Frank said his group had to use another company's extraction technology and database management software on the design, rather than IE's capabilities.

Tom McLaughlin, staff ASIC design engineer at Amber Networks, discussed a 6 million-gate network processor his group successfully created using PKS. But that design was too complex for Cadence's 32-bit timing analyzer and Amber had to use Synopsys' 64-bit PrimeTime offering, McLaughlin added.

Still, McLaughlin said he likes the idea of an all-in-one tool. "I'd be worried if I had to use one vendor's tools for placement and another's for detailed routing," he said.

Thad McCracken, the technical leader at GeoCast Network Systems Inc., said his design group used PKS to develop a family of MIPS-based controllers ranging from 1 million to 6 million transistors, processed in 0.18?m technology. PKS timing estimates were within 3 percent accuracy of silicon, he said.

Meanwhile, competitors said they were unimpressed with the new Cadence offering. "While IE is being positioned as a single tool, what it seems to constitute is Cadence's third attempt at a 'design framework,' " said Sanjiv Kaul, senior vice president and general manager of physical synthesis at Synopsys, which has its own detailed routing system under development and will soon offer head-on competition for IE.

Three years behind

Cadence is three years behind Avanti when it comes to fielding a single-database solution, said Michael Jackson, head of western engineering for Avanti Corp. "I was amazed to see how similar their plan paralleled Avanti's SinglePass-SoC solution," he said.

On the other hand, with its recent Blast Chip announcement-which includes RTL synthesis-Magma Design Automation has the offering closest to IE. "With a single unified data model, Magma's Blast Fusion has consistently delivered better results in customer benchmarks than PKS-IE's cornerstone technology-in all measures including timing, die size, capacity and run-time," said Bob Smith, vice president of marketing and business development for Magma.

However, Jeff Roane, vice president of marketing for Cadence's SP&R group, dismissed his competitors' claims. Speaking of Magma, he said, "I'm hard-pressed to find any evidence of products that substantiate their claims. I think the industry suffers from a lack of real tools that are available today for customers to use," Roane said.

? Michael Santarini and Richard Goering

EE Times





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